| Patch | Description | Author | Forwarded | Bugs | Origin | Last update |
|---|---|---|---|---|---|---|
| 0001-Translate-atomic_fetch_sub-to-OpAtomicFAddEXT-with-n.patch | [PATCH 001/172] Translate atomic_fetch_sub to OpAtomicFAddEXT with negative value operand (#1506) Backport for https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1492 |
Haonan Yang <haonan.yang@intel.com> | no | 2022-06-16 | ||
| 0002-Move-SPV_INTEL_memory_access_aliasing-tokens-from-sp.patch | [PATCH 002/172] Move SPV_INTEL_memory_access_aliasing tokens from spirv_internal SPV_INTEL_memory_access_aliasing is implemented inside SPIRV-Headers and moved out from spirv_internal.hpp (cherry picked from commit a46d8a65cbadc1defa1a2815cd53630699af986e) |
DmitryBushev <dmitry.bushev@intel.com> | no | 2022-02-08 | ||
| 0003-Fix-SPIRV-OCL-barrier-call-argument-attributes-1407.patch | [PATCH 003/172] Fix SPIRV -> OCL barrier call argument attributes (#1407) The first arg of CI is not used as arg in NewCI. So its attribute should be removed from attributes of NewCI. (cherry picked from commit f797de28e4f2d87e0f401faa453460f1e6e5a7ee) |
Wenju He <wenju.he@intel.com> | no | 2022-02-18 | ||
| 0004-Translate-function-attributes-incl.-parameter-attrs-.patch | [PATCH 004/172] Translate function attributes (incl. parameter attrs) for entry point kernels (#1409) * Restore `noalias` parameter attribute test check, removed in 7f168b27. * Restore the translation of function attributes and function parameter attributes for entry point kernels, accidentally dropped in 85815e7 "add an entry point wrapper around functions". (cherry picked from commit aded5afb04f02b1b057db96cd9a8a5e9d1ff47fc) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2022-02-25 | ||
| 0005-Support-SPV_INTEL_non_constant_addrspace_printf-1364.patch | [PATCH 005/172] Support SPV_INTEL_non_constant_addrspace_printf (#1364) (cherry picked from commit 6e70d1c7788f67557fc6148b7b5113e2b500635e) |
Nikita <nikita.kornev@intel.com> | no | 2022-02-28 | ||
| 0006-Improve-lit-tests-replace-hardcoded-parameters-with-.patch | [PATCH 006/172] Improve lit tests: replace hardcoded parameters with more robust and reliable values (#1431) (cherry picked from commit 7de9b5bb7b2fedbaf218c401043e999e01e33056) |
Andrey Tretyakov <andrey1.tretyakov@intel.com> | no | 2022-03-05 | ||
| 0007-Improve-lit-tests-added-missed-parameters-to-make-it.patch | [PATCH 007/172] Improve lit tests: added missed parameters to make its more robust and reliable (#1430) (cherry picked from commit 3ec8fedb74bb124f8e71c5432ba80f0497b48c50) |
Andrey Tretyakov <andrey1.tretyakov@intel.com> | no | 2022-03-05 | ||
| 0008-Replace-assertions-with-friendlier-checkError-in-tra.patch | [PATCH 008/172] Replace assertions with friendlier checkError() in `transMetadataDecorations()` (#1422) (cherry picked from commit 1538cf59bb1f4db549cd7ec9ebb65b5db1875144) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2022-03-05 | ||
| 0009-Fix-argument-attributes-for-SPIRV-OCL-group-builtins.patch | [PATCH 009/172] Fix argument attributes for SPIRV -> OCL group builtins (#1412) The first argument or first two arguments are not used as arguments in new call instruction to OCL group builtins, so the related attributes should be removed from attributes of new call instruction. (cherry picked from commit b5b102e58f55a58f33599400d0d9f80adb6dcc85) |
Feng Zou <feng.zou@intel.com> | no | 2022-03-11 | ||
| 0010-Fix-translation-for-matrix-slicing-with-bfloat16-142.patch | [PATCH 010/172] Fix translation for matrix slicing with bfloat16 (#1427) (cherry picked from commit fd9d8f36b0886006eefe7a9bac6509d296c4744d) |
Leonid Pauzin <leonid.pauzin@intel.com> | no | 2022-03-11 | ||
| 0011-NFC-Replace-CHECK-to-CHECK-DAG-in-new-test-1435.patch | [PATCH 011/172] [NFC] Replace CHECK to CHECK-DAG in new test (#1435) (cherry picked from commit aa867b76a78a3ce79f7d2abe81857f9c9c2c607a) |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-03-11 | ||
| 0012-Support-SPV_KHR_uniform_group_instructions-extension.patch | [PATCH 012/172] Support SPV_KHR_uniform_group_instructions extension (#1253) This extension adds eight new uniform instructions in SPIR-V to enable additional group operations. SPIR-V Headers: KhronosGroup/SPIRV-Headers#269 SPIR-V Tools: KhronosGroup/SPIRV-Tools#4734 (cherry picked from commit 950ce8ffa9727925214c2ea71c3465dff71e410f) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-16 | ||
| 0013-Fix-annotation-translation-when-the-value-is-0-1436.patch | [PATCH 013/172] Fix annotation translation when the value is 0 (#1436) * Fix annotation translation when the value is 0 * Add additional checks and fix comment (cherry picked from commit a9b9ca0bb995949fc3b4a04627857a3ae4e74979) |
Leonid Pauzin <leonid.pauzin@intel.com> | no | 2022-03-17 | ||
| 0014-Support-complex-recursive-types-that-use-an-array-of.patch | [PATCH 014/172] Support complex recursive types that use an array of pointers (#1434) The use of pointer arrays inside the recursive type leads to the SPIR-V IR, where the TypePointer is declared after TypeArray. In turn, TypeArray can't handle the unknown element type, because the info from TypeForwardPointer is not used. Now the translator stores forward declared IDs to use them in backward translation. It actually means that the translator "knows" about the type but it would be handled later. (cherry picked from commit 8a0235a239f34a19136eafd88c7f515537bab40a) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2022-03-22 | ||
| 0015-Remove-Bitcast-llvm.memset-optimization-in-reverse-t.patch | [PATCH 015/172] Remove Bitcast -> llvm.memset optimization in reverse translation (#1447) It is done in order to avoid llvm.memcpy -> llvm.memset transformation which can be an incorrect assumption. SPIR-V does not have a memset instruction, there is a direct mapping only for `llvm.memcpy` to `OpCopyMemory*`. To handle `llvm.memset`, the input LLVM IR is lowered by `SPIRVRegularizeLLVM` pass. The mentioned optimization tried to restore the memset instruction but it surely does not cover all the possible cases (e.g., memcpy is not a memset inst). Possibly, the number of follow-up fixes for different corner cases can prove that the optimization is not absolutely correct, and it's better to rely on regularize pass. (cherry picked from commit cebaf79ef2a2c228d08c278db850a08874273060) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2022-03-22 | ||
| 0016-Align-group-instructions.ll-test-with-the-spec-1448.patch | [PATCH 016/172] Align group-instructions.ll test with the spec (#1448) According to https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_uniform_group_instructions.asciidoc the OpGroupLogicalAnd/Or/Xor X argument and the result type must be scalar/vector of bool. (cherry picked from commit a6a1d4c7d453c1f54d6437f167a002c25b27c561) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-22 | ||
| 0017-Fix-invalid-substitutions-in-test.patch | [PATCH 017/172] Fix invalid substitutions in test %break etc are not valid substitutions for llvm-lit. (cherry picked from commit 3b00f155ae4061c15a26748d4b20a8a336d6a393) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-03-22 | ||
| 0018-Fix-wrong-DICompositeType-size-1452.patch | [PATCH 018/172] Fix wrong DICompositeType size (#1452) If count = -1 we shouldln't cast it to unsigned (cherry picked from commit 1c0bc1c9cefff9bc539185139bd990b20153b774) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-29 | ||
| 0019-Support-SPV_INTEL_complex_float_mul_div-extension-14.patch | [PATCH 019/172] Support SPV_INTEL_complex_float_mul_div extension (#1442) (cherry picked from commit bc94b7c3a637446748072a9e7fd883724bd6b4e5) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-29 | ||
| 0020-Expand-annotation-carried-decoration-parsing-1446.patch | [PATCH 020/172] Expand annotation-carried decoration parsing (#1446) The SPIR-V translator currently allows LLVM IR annotation intrinsics to carry a selection of INTEL extension decorations as part of the string in its second argument. These changes expand the parsing of these to allow generic parsing of decorations in annotation strings, identifying the decorations by their SPIR-V integer identifiers rather than reserved names. It is legal to have decorations with reserved named specified by their SPIR-V integer identifiers, but to allow backwards compatibility the reverse translation will use the reserved names for all decorations with them. (cherry picked from commit f50abe3ace6b61a82b045b88cffbfa6c1c2a3615) |
Steffen Larsen <steffen.larsen@intel.com> | no | 2022-03-29 | ||
| 0021-Allow-OpenCL-builtins-mangling-for-non-standard-prec.patch | [PATCH 021/172] Allow OpenCL builtins mangling for non-standard precision integer (#1451) (cherry picked from commit 5d2586dcb2d49250ce22343aee4c65a762c67f40) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-29 | ||
| 0022-Extend-bool-arg-of-shift-operations-1450.patch | [PATCH 022/172] Extend bool arg of shift operations (#1450) This is a patch to regularize lshr instruction with an i1 argument. According to the SPIR-V specification OpShiftRightLogical operands should be of integer type. (cherry picked from commit c65f1902d9fc468662c08f62a07488108d8625c2) |
Nikita <nikita.kornev@intel.com> | no | 2022-03-29 | ||
| 0023-Modify-getPointerElementType-calls-1457.patch | [PATCH 023/172] Modify getPointerElementType calls (#1457) (cherry picked from commit b298bf44433891c9a2b31d078e96f327374848e6) |
Leonid Pauzin <leonid.pauzin@intel.com> | no | 2022-03-30 | ||
| 0024-Fix-umul.with.overflow.ll-test-fails-1458.patch | [PATCH 024/172] Fix umul.with.overflow.ll test fails (#1458) (cherry picked from commit 28a37e6c601f425b11e4aeac7764e3aab22cec22) |
Leonid Pauzin <leonid.pauzin@intel.com> | no | 2022-03-31 | ||
| 0025-Add-Use-parameter-to-TypeJointMatrixINTEL-1456.patch | [PATCH 025/172] Add 'Use' parameter to TypeJointMatrixINTEL (#1456) 'Use' is an optional parameter that shows where in a math operation the matrix is used. It must be the result of a constant instruction with scalar 'integer type'. (cherry picked from commit 348da245f39bd5292f54d164585ceb8a8ffc4933) |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-04-01 | ||
| 0026-Migrate-SPIRVReader-to-new-PassManager.patch | [PATCH 026/172] Migrate SPIRVReader to new PassManager (cherry picked from commit 4611812b3b12f37fb69817c0dccd7b06389d0d7a) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-03-30 | ||
| 0027-Add-assertation-for-FenceInst-translation-1460.patch | [PATCH 027/172] Add assertation for FenceInst translation (#1460) (cherry picked from commit 16acbd8964f4cb693d95675875c1a37e47519093) |
Leonid Pauzin <leonid.pauzin@intel.com> | no | 2022-04-04 | ||
| 0028-Support-translation-of-uniform-group-extension-instr.patch | [PATCH 028/172] Support translation of uniform group extension instructions form SPIRV to OCL (#1459) (cherry picked from commit f11e3a8db8477987f1778890d23eeecf7850c045) |
Wenwan Xing <wenwan.xing@intel.com> | no | 2022-04-06 | ||
| 0029-Fix-sret-attribute-to-be-valid-LLVM-IR.patch | [PATCH 029/172] Fix sret attribute to be valid LLVM IR. The sret attribute is supposed to indicate what would be the pointee type of the parameter (to support the transition to opaque pointers). Somehow, the original change to this code concluded it was supposed to be a pointer type instead, however, for the sret attribute, while the byval attribute was correctly handled. (cherry picked from commit a6cbadeef4fcb49329d3794e5faa043df830a1dc) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-04-13 | ||
| 0030-.clang-tidy-allow-recursion.patch | [PATCH 030/172] .clang-tidy: allow recursion The code already uses recursion in various places and this check fails whenever a change is made in the recursion chain. (cherry picked from commit 28fdb7ace62ac33af43374f8e52f6479073ae594) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-04-20 | ||
| 0031-Replace-uses-of-Type-getPointerElementType-in-SPIRVR.patch | [PATCH 031/172] Replace uses of Type::getPointerElementType in SPIRVReader. (cherry picked from commit 07a7cca091b7f43d1194095d3dcc7e5e8b43d29b) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-04-21 | ||
| 0032-CI-Temporarily-allow-use-of-deprecated-functions.patch | [PATCH 032/172] [CI] Temporarily allow use of deprecated functions LLVM commit c99424f76560 ("[IR] Deprecate Type::getPointerElementType() (NFC)", 2022-04-20) caused out-of-tree builds to fail (as these use `-Werror`). Replacing all `Type::getPointerElementType` calls is a longer term effort so turn deprecation errors back into warnings to resume out-of-tree builds. (cherry picked from commit 55d1de820841e6d9d1c6ca0cd534323d69a1cbf1) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-04-22 | ||
| 0033-Remove-more-getPointerElementType-queries.patch | [PATCH 033/172] Remove more getPointerElementType queries. Most of this tranche of calls were being used to disambiguate between different built-ins that share the same or similar names. The exception is the change in visitCallSPIRVPipeBuiltin, which is a convoluted way of adding a cast to i8 addrspace(4)* if not already i8 addrspace(4)*, so it is instead rewritten to check if a cast needs to be added without querying getPointerElementType. (cherry picked from commit f727f4d191a766c7c82b5f5ea90be052335fb01a) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-04-22 | ||
| 0034-Remove-LowerSPIRBlocks-pass-as-it-appears-to-be-obso.patch | [PATCH 034/172] Remove LowerSPIRBlocks pass, as it appears to be obsolete. (cherry picked from commit 1555107a27ddc49bf2f4b7c4cdb54e24616445bf) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-05-09 | ||
| 0035-Make-the-LowerBitCast-pass-support-opaque-pointers.patch | [PATCH 035/172] Make the LowerBitCast pass support opaque pointers. This is a relatively large change, as the original pass relied on being able to track the initial bitcast <3 x i64>* to <6 x i32>* to know where to start rewriting. Instead, this patch starts at the final invalid extractelement call and works its way backwards as far as necessary to generate correct code. (cherry picked from commit 83b2dfd317d99481aac7c5e8521259096e2207c2) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-05-04 | ||
| 0036-NFC-Avoid-excess-runs-of-OCLTypeToSPIRV.patch | [PATCH 036/172] [NFC] Avoid excess runs of OCLTypeToSPIRV OCLTypeToSPIRV is an analysis required by other passes, so we don't need to run it explicitly. (cherry picked from commit 3cbf128f157eb82ac7eced76029842beff7bd828) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-19 | ||
| 0037-NFC-Fix-mangled-names-in-test.patch | [PATCH 037/172] [NFC] Fix mangled names in test `clang/lib/AST/ItaniumMangle.cpp` doesn't include any `_t` in the mangled name. (cherry picked from commit d06c92387d49488af574c650a57d4fcfba881115) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-19 | ||
| 0038-Remove-function-pointer-cast-deletion-in-SPIRVRegula.patch | [PATCH 038/172] Remove function pointer cast deletion in SPIRVRegularizeLLVM. It seems to be another remnant of earlier versions of dealing with block types, as it is looking for SPIR-V builtins that have function pointer arguments. With blocks now represented as structs, it seems that nothing will trigger this code any more. In any case, with opaque pointers, this code becomes unnecessary (as the bitcasts that would be deleted won't exist anymore). (cherry picked from commit 1341e546a89e0f519eb8236e096bd14603474e96) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-05-18 | ||
| 0039-Remove-a-few-more-getPointerElementType-calls.patch | [PATCH 039/172] Remove a few more getPointerElementType() calls. The change in getScalarOrArrayConstantInt() is not actually exercised by the current test suite, and it may be impossible to exercise it given that the caller of the function relies on the parameter being a GEP of array type. However, this change should correctly deduce the type were it a correct call. The call in SPIRVRegularizeLLVM is of course unnecessary with opaque pointers: addrspacecast can never change the pointee type of a pointer type in such scenarios. (cherry picked from commit 4b415cb78076690b3c8ea513a2843a6c7f466e9c) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-05-09 | ||
| 0040-NFC-Preparations-to-rename-the-default-branch.patch | [PATCH 040/172] [NFC] Preparations to rename the default branch (cherry picked from commit 22cf0eace5e29f5506a96e39acf3fea465eff18a) |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-03-26 | ||
| 0041-CI-Update-for-branch-rename.patch | [PATCH 041/172] [CI] Update for branch rename (cherry picked from commit 6db0f312c918bba14a731822b38a18726bb4ce09) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-31 | ||
| 0042-Fix-some-typos.patch | [PATCH 042/172] Fix some typos (cherry picked from commit 24c5671d54f899f159047779097865822ea302c5) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-31 | ||
| 0043-Recover-SPIR-V-opaque-types-from-demangling-function.patch | [PATCH 043/172] Recover SPIR-V opaque types from demangling function names. (#1477) The centerpiece of this patch is the addition of getParameterTypes function, which will parse out the pointee struct types using LLVM's built-in Itanium demangling interface (which is unfortunately not easy to use). Passing this information along via llvm StructTypes was chosen to minimize the impact of this change on caller code; it is likely that a future cleanup patch to use an enum or similar mechanism to represent possible SPIR-V struct types would be advisable. A side effect of this change is that several helper methods that query pointer element types can be eliminated, which does lead to some cleanup that got tangled up in the demangler-enabling work. Extra function calls to getPointerElementType() are temporarily added to disentangle this patch from work moving OCLTypeToSPIRV to store pointee types rather than pointer types; this will likely be fixed as part of the effort to get SPIRVWriter working with opaque pointer types. (cherry picked from commit 76e181ec6de56d8b24d509c0c39691e9754fb1b5) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-06-07 | ||
| 0044-NFC-Move-pass-declarations-into-separate-header-file.patch | [PATCH 044/172] [NFC] Move pass declarations into separate header files Prepare for migrating SPIRVWriter to the new PassManager by making sure the new non-legacy pass declarations are visible outside of their .cpp file. (cherry picked from commit 337b171131b13487e280752c92508ded4291aff6) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-20 | ||
| 0045-Remove-using-namespace-llvm-from-some-headers.patch | [PATCH 045/172] Remove 'using namespace llvm' from some headers (cherry picked from commit 8546d9924536e1b351cd04dbe6b83f02f62fc045) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-08 | ||
| 0046-NFC-Use-only-one-PassManager-in-SPIRVWriter.patch | [PATCH 046/172] [NFC] Use only one PassManager in SPIRVWriter Factor out common code, in preparation of transitioning SPIRVWriter to the new PassManager. (cherry picked from commit dc9e645917b106332cdf46a790a9481d44282a96) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-09 | ||
| 0047-NFC-Alignment-Use-getAlign-in-SPIRVWriter.patch | [PATCH 047/172] [NFC][Alignment] Use getAlign in SPIRVWriter LLVM is removing the getAlignment method from LoadInst and StoreInst in these commits: * https://github.com/llvm/llvm-project/commit/8865700f905173b71932cc241b5d36600343f425 * https://github.com/llvm/llvm-project/commit/2b89a4dc51d539cefd3628775883a32c9dd6fc64 This change fixes build errors with these LLVM changes by replacing the remaining uses of getAlignment in SPIRVWriter with getAlign. (cherry picked from commit e4862b74c8157b0192385a760392a39afabdd48c) |
Daniel Woodworth <daniel.woodworth@intel.com> | no | 2022-06-13 | ||
| 0048-Update-for-AllocaInst-getAlignment-API-removal.patch | [PATCH 048/172] Update for AllocaInst::getAlignment API removal Update for LLVM commit b4cf74dc9e85 ("[NFC] Remove dead code", 2022-06-14) which removed the getAlignment method. (cherry picked from commit 1c435a82c1b6a3f3570bbdb67d23c878bb779670) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-14 | ||
| 0049-Update-SPIRV-Headers.patch | [PATCH 049/172] Update SPIRV-Headers Update the SHA-1 of the SPIRV-Headers dependency to 5a121866927. Regenerate the header files using the newer spirv.hpp. The generated .h files had to be tweaked manually due to various internal additions. (cherry picked from commit 3f5e65d55e451f459259afcfe012f834d4fadf59) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-14 | ||
| 0050-Prepare-SPIRVWriter-for-type-conversion-without-opaq.patch | [PATCH 050/172] Prepare SPIRVWriter for type conversion without opaque pointers. (#1499) This changeset is, by itself, not yet enough to get most SPIR-V files to be emitted when the input module is in opaque pointer mode. However, this does remove all of the calls to `getPointerElementType` that SPIRVWriter makes (directly or indirectly), except for the ones that directly correspond to translating a pointer type. A later changeset will add a type scavenger that will be used to find the pointee type of a pointer. All calls to `getPointerElementType` that remain after this one will be instead shifted to query the type scavenger instead. To facilitate this change, several methods are added to avoid querying pointer element types, and they have been added in several places where their need is known. The most basic of basic kernels, those that do not use pointer types (other than declaring global values and functions) will work in opaque pointer mode with this changeset. (cherry picked from commit 4a9c78eea1561c55e9acbded1c2e9b3181f7b971) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-06-20 | ||
| 0051-Clear-OCLTypeToSPIRV-at-start.patch | [PATCH 051/172] Clear OCLTypeToSPIRV at start The pass is no longer being reallocated after each run when running from the new PassManager. (cherry picked from commit b21bd84cf3a50ef315c13097c4abac78ce580c41) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-05-19 | ||
| 0052-Initialize-some-member-variables.patch | [PATCH 052/172] Initialize some member variables (cherry picked from commit eb53f79d1b830fb7c1d70271a20106b84c412276) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-13 | ||
| 0053-Migrate-SPIRVWriter-to-new-PassManager.patch | [PATCH 053/172] Migrate SPIRVWriter to new PassManager (cherry picked from commit eb8e9adc7b05ab89c59b63286e4a34f188748b59) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-13 | ||
| 0054-Fix-build-by-reverting-a-ValueMap-back-to-std-map.patch | [PATCH 054/172] Fix build by reverting a ValueMap back to std::map Commit 4a9c78ee ("Prepare SPIRVWriter for type conversion without opaque pointers. (#1499)", 2022-06-20) changed `OCLTypeToSPIRVBase::AdaptedTy` to a `ValueMap`, but that made `OCLTypeToSPIRVBase` non-movable and non-copyable. Landing eb8e9adc ("Migrate SPIRVWriter to new PassManager", 2022-06-20) on top caused a build breakage. (cherry picked from commit 2a8f52469527346c8cc3cf12371a2fe7592e285f) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-20 | ||
| 0055-Add-SPV_KHR_subgroup_rotate-support.patch | [PATCH 055/172] Add SPV_KHR_subgroup_rotate support Add support for mapping the SPV_KHR_subgroup_rotate extension operations to and from SPIR-V friendly IR, as well as to and from the cl_khr_subgroup_rotate OpenCL extension. Specifications: - https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_subgroup_rotate.html - https://www.khronos.org/registry/OpenCL/specs/3.0-unified/html/OpenCL_Ext.html#cl_khr_subgroup_rotate (cherry picked from commit a49de2a30cb31cd4e2e7643eb62f5f98feae1756) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-15 | ||
| 0056-Fix-excess-kernel_arg_type_qual-entry-in-test.patch | [PATCH 056/172] Fix excess kernel_arg_type_qual entry in test The metadata had 7 entries whereas the function only has 6 parameters, causing foreachKernelArgMD to read past the end of an std::vector. (cherry picked from commit 14b843b6a5af382c43a2e2d999a5f57614d49812) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-22 | ||
| 0057-Fix-UB-when-validating-spirv-ext-option.patch | [PATCH 057/172] Fix UB when validating spirv-ext option When passing `spirv-ext=,`, SPVExt will contain empty strings. Calling `front` on an empty string is undefined behavior, so first ensure that the string is not empty. (cherry picked from commit 30fb15c11f0dc5be04fddb0b3798098ca1ee0ea4) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-22 | ||
| 0058-CMake-Enable-LLVM_BUILD_TOOLS-for-out-of-tree-builds.patch | [PATCH 058/172] [CMake] Enable LLVM_BUILD_TOOLS for out-of-tree builds This ensures the llvm-spirv tool is added to the "all" target, so that it is included when installing the project. (cherry picked from commit ae904012e2739fa152412e0f1bfc8eb32a808854) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-15 | ||
| 0059-CI-Exclude-some-files-from-code-style-checks.patch | [PATCH 059/172] [CI] Exclude some files from code style checks Some files cannot be parsed on their own as they for example require a macro to be defined. To avoid spurious failures of clang-tidy, exclude such files from the code style checks. Remove spirv.hpp from the list as it is no longer in the tree. (cherry picked from commit 09749079fb73f3b0e799adf7955dfbb8bb63afb4) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-28 | ||
| 0060-NFC-Restrict-access-to-some-SPIRVToOCLBase-members.patch | [PATCH 060/172] [NFC] Restrict access to some SPIRVToOCLBase members (cherry picked from commit 47f96697182d8f65d28e59f690a5b5b7d3d0949f) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-27 | ||
| 0061-NFC-Factor-out-mutateArgsForImageOperands.patch | [PATCH 061/172] [NFC] Factor out mutateArgsForImageOperands (cherry picked from commit 2892a1ec1bab23a95dd0fe14eb8527c95ad5c2d6) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-27 | ||
| 0062-NFC-Separate-image-operand-and-LoD-handling.patch | [PATCH 062/172] [NFC] Separate image operand and LoD handling (cherry picked from commit 82f31a38e4de7c98287ee01e605af3a7011cd726) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-27 | ||
| 0063-Fix-some-mangling-bugs-in-the-Itanium-name-mangler.patch | [PATCH 063/172] Fix some mangling bugs in the Itanium name mangler. Substitution rules in Itanium mangled names are unfortunately more complex and harder to parse than they should be, and there were two bugs that cropped in the current implementation (as found by running c++filt on the resulting names and discovering that they didn't demangle correctly). The first bug was that unqualified names double-registered the underlying pointer type. A mangled pointer type like PU3AS419__spirv_DeviceEvent should generate three substitutable names: * 19__spirv_DeviceEvent [a user-defined type gets an entry] * U3AS419__spirv_DeviceEvent [qualifiers of a pointer get an entry] * PU3AS419__spirv_DeviceEvent [the pointer as a whole gets an entry] However, if there's no qualifiers--we get a P19__spirv_DeviceEvent instead-- the original code was still adding multiple entries as follows: * 19__spirv_DeviceEvent [a user-defined type gets an entry] * 19__spirv_DeviceEvent [qualifiers of a pointer, but there are none!] * P19__spirv_DeviceEvent [the pointer as a whole gets an entry] The second bug is in the representation of the block pointer type for kernels: this is mangled as U13block_pointerFvvE. This type actually gets two entries: * FvvE [void(void) function type] * U13block_pointerFvvE [block_pointer-qualified function type] We weren't adding any entries for either of these types, causing later type entries to be offset by two. With this patch, these type entries *still* aren't added, so the mangling is incorrect if multiple block types are present in a function declaration. Since such functions don't exist for OpenCL/SPIR-V, it's okay that these cases are not correctly handled. (cherry picked from commit 9b280f4ed0720031afff35ea9578cc0c0b132d2b) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-07-01 | ||
| 0064-Implement-support-for-llvm.sadd.sat-intrinsic.-1524.patch | [PATCH 064/172] Implement support for @llvm.sadd.sat intrinsic. (#1524) * Implement support for @llvm.sadd.sat intrinsic. * Rename LowerSaddWithOverflow to LowerSaddIntrinsics. (cherry picked from commit 0af7e643bb8eb4c94ef336ef0f4ae3a10321e763) |
Joshua Cranmer <joshua.cranmer@intel.com> | no | 2022-07-08 | ||
| 0065-NFC-Use-mutateArgsForImageOperands-for-SPIRVImageRea.patch | [PATCH 065/172] [NFC] Use mutateArgsForImageOperands for SPIRVImageReadBuiltIn (cherry picked from commit 18d1f41f4d168bf3ea99263155e83350016bb6fe) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-29 | ||
| 0066-Use-Sign-ZeroExtend-image-operands-for-read-write_im.patch | [PATCH 066/172] Use Sign/ZeroExtend image operands for read/write_image Emit (in OCLToSPIRV) and decode (in SPIRVToOCL) the SignExtend and ZeroExtend Image Operands introduced by SPIR-V version 1.4 to preserve signedness of image read and write operations. This allows distinguishing between e.g. `read_imagei` and `read_imageui` and enables a lossless LLVM -> SPIR-V -> LLVM conversion for those OpenCL builtins. Before SPIR-V 1.4, there was no way to represent the signedness of the image operations and llvm-spirv defaulted to signed. This commit leaves that behaviour unchanged if llvm-spirv's maximum version is set to SPIR-V 1.3 or below. Add the `--spirv-max-version=1.3` flag to some tests that rely on the old behaviour. (cherry picked from commit bb4ead0d84870afe1f6f4ce829ba985b1b7950c7) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-06-29 | ||
| 0067-Fix-out-of-bounds-access-in-SPIRVToOCLBase-mutateArg.patch | [PATCH 067/172] Fix out of bounds access in SPIRVToOCLBase::mutateArgsForImageOperands When called from visitCallSPIRVImageReadBuiltIn, Args only has three elements and ImOpArgIndex is 2. This has been causing this function to "update" an argument past the end of the vector, which caused a crash when running transcoding/image_signedness.ll on Windows because the debug build in Windows has bounds checking on std::vector. With this change, it should update the correct (and not past the end) argument instead and satisfy the Windows bounds checks. (cherry picked from commit 6904b388c1a115dbb634b9a194091af84e191a39) |
Daniel Woodworth <daniel.woodworth@intel.com> | no | 2022-07-13 | ||
| 0068-Fix-integer-dot-product-translation-1174.patch | [PATCH 068/172] Fix integer dot product translation (#1174) Fix translation of IR from source when dot function is called with integer arguments (ints, vectors of chars or shorts) to properly support cl_khr_integer_dot_product extension. Previously it translated calls such as dot(uchar4, uchar4) into OpDot %i8, which is wrong because OpDot only operates on floating point types. (cherry picked from commit c8cd2f6895091f84823d94a661753c0a9765a7a7) |
Jakub Czarnecki <jakub.czarnecki@intel.com> | no | 2022-07-22 | ||
| 0069-Restore-argument-tracing-in-OCLTypeToSPIRV.patch | [PATCH 069/172] Restore argument tracing in OCLTypeToSPIRV Commit 4a9c78ee ("Prepare SPIRVWriter for type conversion without opaque pointers. (#1499)", 2022-06-20) removed `getArgIndex` in favor of passing `Idx`, but this leads to incorrect adaptation of argument types if sampler arguments are not in the same position between different functions. We might be able to drop `adaptArgumentsBySamplerUse` entirely, as we don't represent samplers as i32 anymore; but for now just fix the regression. Fixes https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/1562 (cherry picked from commit 87f8a58252ff91a75c524362f3dd4d452872108e) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-08-08 | ||
| 0070-Dot-product-bugfix-to-include-more-floating-point-ty.patch | [PATCH 070/172] Dot product bugfix to include more floating point types (#1578) (#1593) Switched the visitCallDot check to use isFloatingPointTy for scalar floating point operands. Bugfix for previous change regarding integer dot product. |
Jakub Czarnecki <jakub.czarnecki@intel.com> | no | 2022-08-23 | ||
| 0071-Backport-to-14-Update-SPV_INTEL_vector_compute-to-re.patch | [PATCH 071/172] [Backport to 14] Update SPV_INTEL_vector_compute to rev 15 This adds NamedBarrierCountINTEL Execution Mode, see more in https://github.com/intel/llvm/pull/1612 |
nrudenko <nikita.rudenko@intel.com> | no | 2020-07-15 | ||
| 0072-Integer-dot-product-4x8-packed-translation.patch | [PATCH 072/172] Integer dot product 4x8 packed translation Changed the integer dot translation to use the correct function names (i.e. dot_4x8packed or dot_acc_sat_4x8packed) to translate them into proper OpCodes. Additionally removed unused variables from visitCallDot |
Jakub Czarnecki <jakub.czarnecki@intel.com> | no | 2022-10-14 | ||
| 0073-Add-support-for-split-barriers-extension-SPV_INTEL_s.patch | [PATCH 073/172] Add support for split barriers extension SPV_INTEL_split_barrier (#1424) (#1662) This PR adds support for split barriers and the SPV_INTEL_split_barrier extension. The related SPIR-V extension spec can be found here: * https://github.com/KhronosGroup/SPIRV-Registry/pull/136 The related OpenCL C extension spec can be found here: * https://github.com/KhronosGroup/OpenCL-Docs/pull/765 |
Haonan Yang <haonan.yang@intel.com> | no | 2022-10-20 | ||
| 0074-CI-Upgrade-to-Ubuntu-20.04.patch | [PATCH 074/172] [CI] Upgrade to Ubuntu 20.04 The Ubuntu 18.04 image is marked deprecated [1], so move to a newer image. [1] https://github.com/actions/runner-images |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-08-18 | ||
| 0075-NFC-Replace-getPointerElementType-in-SPIRVRegularize.patch | [PATCH 075/172] [NFC] Replace getPointerElementType in SPIRVRegularizeLLVM | "Sidorov, Dmitry" <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0076-NFC-Initialize-a-variable.patch | [PATCH 076/172] [NFC] Initialize a variable | "Sidorov, Dmitry" <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0077-CI-Travis-Upgrade-to-Ubuntu-20.04.patch | [PATCH 077/172] [CI][Travis] Upgrade to Ubuntu 20.04 The Ubuntu 18.04 image is marked deprecated [1], so move to a newer image. [1] https://github.com/actions/runner-images |
"Sidorov, Dmitry" <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0078-Backport-to-14-Add-SPV_INTEL_masked_gather_scatter-e.patch | [PATCH 078/172] [Backport to 14] Add SPV_INTEL_masked_gather_scatter extension (#1580) (#1694) This extension allows TypeVector to have a Physical Pointer Type Component Type and introduces gather/scatter instructions. It will be useful for explicitly vectorized kernels. |
Stanley Gambarin <stanley.gambarin@intel.com> | no | 2022-11-12 | ||
| 0079-Backport-to-14-Translate-llvm.loop.unroll.full-metad.patch | [PATCH 079/172] [Backport to 14] Translate llvm.loop.unroll.full metadata (#1674) It can be generated via #pragma clang unroll(full) pragma. llvm.loop.unroll.full means attempt to do full unroll of the loop and disable the unrolling if the trip count is not known at compile time. Unroll mask to which it was previously mapped doesn't much the description. The way the patch represents it in SPIR-V is: Unroll mask + PartialCount mask with '1' parameter This patch also removes some overtesting for unroll metadata. This backports: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1664 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-14 | ||
| 0080-Backport-to-14-Implement-SPV_INTEL_tensor_float32_co.patch | [PATCH 080/172] [Backport to 14] Implement SPV_INTEL_tensor_float32_conversion extension (#1656) (#1701) This extension adds conversion instruction from float to tensor float (TF32) data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead instruction below uses 32-bit float type to represent TF32 value. |
Stanley Gambarin <stanley.gambarin@intel.com> | no | 2022-11-14 | ||
| 0081-Backport-to-14-Fix-builtin-vars-translation.patch | [PATCH 081/172] [Backport to 14] Fix builtin vars translation The translator was crashing in case if builin GV was accessed via GEP without AS cast due to incorrect assumption. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-29 | ||
| 0082-Backport-to-14-Relax-OpenCL-extended-instruction-res.patch | [PATCH 082/172] [Backport to 14] Relax OpenCL extended instruction restrictions (#1724) When VectorAnyINTEL capability is enabled, OpenCL extended instructions are able to work on vector types with any number of components greater then or equal to 2. |
Victor Mustya <victor.mustya@intel.com> | no | 2022-11-23 | ||
| 0083-Backport-to-14-Translate-LLVM-intrinsics-into-native.patch | [PATCH 083/172] [Backport to 14] Translate LLVM intrinsics into native_* OpenCL instructions (#1729) When an intrinsic function is called with `afn` flag, it's allowed to substitute an approximate calculations. So the translator can emit native versions of OpenCL extended instructions. |
Victor Mustya <victor.mustya@intel.com> | no | 2022-11-24 | ||
| 0084-Backport-to-14-Add-SPV_EXT_relaxed_printf_string_add.patch | [PATCH 084/172] [Backport to 14] Add SPV_EXT_relaxed_printf_string_address_space ext The original change #1749 The extension was added in https://github.com/KhronosGroup/SPIRV-Registry/pull/148 Starting from this PR SPV_INTEL_non_constant_addrspace_printf will be step by step deprecated. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-12-02 | ||
| 0085-Deprecate-SPV_INTEL_non_constant_addrspace_printf-ex.patch | [PATCH 085/172] Deprecate SPV_INTEL_non_constant_addrspace_printf extension (#1818) This change continues #1749. We are removing SPV_INTEL_non_constant_addrspace_printf extension in favor of SPV_EXT_relaxed_printf_string_address_space, which are basically the same. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-01-21 | ||
| 0086-Backport-to-14-Translate-readnone-attribute-as-funct.patch | [PATCH 086/172] [Backport to 14] Translate readnone attribute as function parameter attribute (#1697) Community restricted readnone, readonly and writeonly attributes to be only function parameter attributes. This patch aligns the translator with llvm.org. It also fixes a bug, when readnone attribute is being mapped to NoWrite SPIR-V function parameter attribute. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0087-Backport-to-14-Put-memory-none-attribute-instead-of-.patch | [PATCH 087/172] [Backport to 14] Put memory(none) attribute instead of readnone (#1746) Instead of creating readnone attributes on each parameter of a function it's better to put just memory(none) which was recently introduced. See https://reviews.llvm.org/D135780 Co-authored by: Zou, Feng <feng.zou@intel.com> |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-29 | ||
| 0088-Allow-ReadNone-and-ReadOnly-as-Function-attributes.patch | [PATCH 088/172] Allow ReadNone and ReadOnly as Function attributes | Stanley Gambarin <stanley.gambarin@intel.com> | no | 2023-02-16 | ||
| 0089-Fix-mangling-of-opcodes-from-SPV_KHR_bit_instruction.patch | [PATCH 089/172] Fix mangling of opcodes from SPV_KHR_bit_instructions in SPV-IR (#1869) (#1874) | Andrzej Ratajewski <andrzej.ratajewski@intel.com> | no | 2023-03-10 | ||
| 0090-Update-spirv-as-invocations-1932.patch | [PATCH 090/172] Update spirv-as invocations (#1932) After SPIRV-Tools commit 2e0f4b52 ("tools: refactorize tools flags parsing. (#5111)", 2023-02-27), spirv-as needs to be told explicitly when reading from stdin. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-31 | ||
| 0091-Backport-to-14-Initial-support-NonSemantic.Kernel.De.patch | [PATCH 091/172] [Backport to 14]Initial support NonSemantic.Kernel.DebugInfo.100 (#1846) This patch implements the initial support for the new debug specification NonSemantic.Kernel.DebugInfo.100. It also introduces support for the new debug instruction DISubrange. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-02-20 | ||
| 0092-Backport-to-14-DebugInfo-Add-Target-Function-optiona.patch | [PATCH 092/172] [Backport to 14][DebugInfo] Add Target Function optional parameter to DebugFunction (#1853) It's being added in KhronosGroup/SPIRV-Registry#186 In DWARF it's used in 'trampoline' functions generated for Fortran external function calls. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-02-23 | ||
| 0093-Backport-to-14-DebugInfo-Add-new-Source-Languages-ta.patch | [PATCH 093/172] [Backport to 14][DebugInfo] Add new Source Languages table used in DebugCompilationUnit (#1854) This extended source language table is used by DebugCompilationUnit instruction when the extension is enabled. It enables support for more languages than exists in a core specification. Enabling of Fortran language also allowed to fix FortranArray test that was originally XFAIL-ed in 9e234d9. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-02-23 | ||
| 0094-Backport-to-14-DebugInfo-Add-an-option-for-NonSemant.patch | [PATCH 094/172] [Backport to 14][DebugInfo] Add an option for NonSemantic.Shader.DebugInfo.100 (#1855) Under this option this extended instruction set will be implemented Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc NonSemantic.Shader.DebugInfo.200 when the name is stable |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-01 | ||
| 0095-Backport-to-14-DebugInfo-Add-DebugTypeArrayDynamic-t.patch | [PATCH 095/172] [Backport to 14][DebugInfo] Add DebugTypeArrayDynamic translation (#1871) This instruction describes a dynamic array, mostly for Fortran 90. Unlike DebugTypeArray it has Data Location, Associated, Allocated and Rank parameters. If the appropriate metadata parameters appear in LLVM IR in DW_TAG_array_type metadata, then such debug type becomes treated as dynamic array by the translator (of course if the appropriate extended instruction set is enabled). Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-08 | ||
| 0096-Backport-to-14-DebugInfo-Support-translation-of-DISt.patch | [PATCH 096/172] [Backport to 14][DebugInfo] Support translation of DIStringType (#1877) This type instruction describes a string, mostly for Fortran 90. Spec: KhronosGroup/SPIRV-Registry#186 |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-10 | ||
| 0097-Backport-to-14-DebugInfo-Support-translation-of-DIMo.patch | [PATCH 097/172] [Backport to 14][DebugInfo] Support translation of DIModule (#1878) This entity represents a module in the programming language, for example a Fortran module. Spec: KhronosGroup/SPIRV-Registry#186 The implementation is the same as for SPV_INTEL_debug_module extension. Spec for extension: https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_debug_module.asciidoc |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-13 | ||
| 0098-Backport-to-14-DebugInfo-Rename-NonSemantic.Kernel.D.patch | [PATCH 098/172] [Backport to 14][DebugInfo] Rename NonSemantic.Kernel.DebugInfo.100 (#1891) To NonSemantic.Shader.DebugInfo.200 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-20 | ||
| 0099-Backport-to-14-DebugInfo-Start-adopting-debug-info-i.patch | [PATCH 099/172] [Backport to 14][DebugInfo] Start adopting debug info instructions for NonSemantic set (#1887) List of changes: All Literal parameters of instructions in OpenCL.DebugInfo.100 are OpConstants in NonSemantic.Shader.DebugInfo.100 and NonSemantic.Shader.DebugInfo.200; SPV_KHR_non_semantic_info is being implicitly added for nonsemantic debug info; |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-21 | ||
| 0100-Backport-to-14-DebugInfo-Add-more-source-languages-a.patch | [PATCH 100/172] [Backport to 14][DebugInfo] Add more source languages and align to spec changes (#1894) | Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-21 | ||
| 0101-Backport-to-14-DebugInfo-Align-Instruction-names-to-.patch | [PATCH 101/172] [Backport to 14][DebugInfo] Align Instruction names to the specification (#1896) This patch fixes the discovered typos in Debug Instruction names, so we can generate spec-conformant SPIR-V module. https://registry.khronos.org/SPIR-V/specs/unified1/DebugInfo.html |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-23 | ||
| 0102-Rename-ConvertFToTF32INTEL-to-RoundFToTF32INTEL.patch | [PATCH 102/172] Rename ConvertFToTF32INTEL to RoundFToTF32INTEL Extension name will be preserved for a while for binary compatibility. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-04 | ||
| 0103-Backport-to-14-Preserve-invalid-SPIRV-source-lang-li.patch | [PATCH 103/172] [Backport to 14] Preserve invalid SPIRV source lang literal in module metadata (#1951) (#1992) Some SPIR-V producers generate invalid source language value (invalid = other than the enum values defined in spv::SourceLanguage). While in many cases this is rightly translated to DW_LANG_OpenCL, the original source language value should be preserved in LLVM module metadata for later use by LLVM IR consumers. |
Andrzej Ratajewski <andrzej.ratajewski@intel.com> | no | 2023-05-04 | ||
| 0104-Backport-to-14-Check-for-nullptr-from-getDbgInst-191.patch | [PATCH 104/172] [Backport to 14]Check for nullptr from getDbgInst (#1919) Ensure that ExprLB is non-NULL before using it. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-03-31 | ||
| 0105-Backport-to-14-DebugInfo-Add-DW_ATE_complex_float-tr.patch | [PATCH 105/172] [Backport to 14][DebugInfo] Add DW_ATE_complex_float translation (#1946) It's mapped on new Encoding value for DebugBasicType in NonSemantic.Shader.DebugInfo.200 spec. If another DebugInfo instruction set is specified - it's mapped to DW_TAG_unspecified_type Spec: KhronosGroup/SPIRV-Registry#186 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-12 | ||
| 0106-Backport-to-14-DebugInfo-Handle-null-value-of-DW_TAG.patch | [PATCH 106/172] [Backport to 14][DebugInfo] Handle null value of DW_TAG_template_value_parameter (#1956) It might be set as null in case if a function pointer is passed as auto template parameter. The patch also adds a test for a 'good' DW_TAG_template_value_parameter value for function pointers, just because this case was untested. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-14 | ||
| 0107-Backport-to-14-DebugInfo-Support-multiple-CompileUni.patch | [PATCH 107/172] [Backport to 14][DebugInfo] Support multiple CompileUnits (#1950) It's possible for LLVM IR module to contain multiple CU in case if this module is a result of llvm-link between two modules compiled for different languages and or compiled with different options. This patch introduces handling of such modules. std::unordered_map<SPIRVId, std::unique_ptr> BuilderMap was introduced to SPIR-V consumption part and std::unordered_map<const DICompileUnit *, SPIRVExtInst *> SPIRVCUMap was introduced to SPIR-V generation part to preserve Scope relations between DI metadata in SPIR-V and vice versa. Note, that DIBuilder has a single CU field and this class is not trivially copiable. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-19 | ||
| 0108-Backport-to-14-DebugInfo-Support-translation-of-Debu.patch | [PATCH 108/172] [Backport to 14][DebugInfo] Support translation of DebugFunctionDefinition instruction (#1961) DebugFunction does not have an Function Id operand in NonSemantic.Shader debug info specification. It's been replaced by the whole new DebugFunctionDefinition instruction to avoid forward references. This instruction must appear in the entry basic block of an OpFunction. Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugFunctionDefinition |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-20 | ||
| 0109-Backport-to-14-DebugInfo-Add-module-producer-info-fo.patch | [PATCH 109/172] [Backport to 14][DebugInfo] Add module producer info for NonSemantic.Shader.DebugInfo.200 (#1968) Keep existing W/A for other debug info specs, except NonSemantic.Shader.DebugInfo.100 |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-21 | ||
| 0110-NFC-Use-typed-pointers-for-null-function-pointers-de.patch | [PATCH 110/172] [NFC] Use typed pointers for null function pointers debug info (#1969) `PointerType::get(Context` will return typeless/opaque pointer. While it is OK for KHR translator since it's being built on top of LLVM trunk, where opaque pointers are enabled by default - it won't work for intel/llvm, where their generation is disabled. Upstream of https://github.com/intel/llvm/pull/9118 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-22 | ||
| 0111-Backport-to-14-DebugInfo-Fix-Composite-type-translat.patch | [PATCH 111/172] [Backport to 14][DebugInfo] Fix Composite type translation for NonSemantic spec (#1975) Tag should be OpConstant, not Literal. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-25 | ||
| 0112-DebugInfo-Add-Flag-parameter-to-DebugTypeBasic-1965.patch | [PATCH 112/172] [DebugInfo] Add Flag parameter to DebugTypeBasic (#1965) It can only be FlagUnknownPhysicalLayout. There is no way we can generate it LLVM environment and get use of it, hence the patch just ignores it if it come from another SPIR-V generator. In general, there are following possible debug flags for DIBasicType: BigEndian, LittleEndian and Artificial. There is not way that clang will ever generate them, but that can be produced by manually writing assembly and transforming it to LLVM IR. While it can be potential improvement for the future - I don't see it useful to add to the spec and implementation right now. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-26 | ||
| 0113-Backport-to-14-DebugInfo-Support-translation-of-Debu.patch | [PATCH 113/172] [Backport to 14][DebugInfo] Support translation of DebugEntryPoint instruction (#1973) This instruction is generated for DWARF `DISPFlagMainSubprogram` flag of function as well as for `spir_kernel` functions. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugEntryPoint |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-26 | ||
| 0114-Backport-to-14-DebugInfo-Add-NonSemantic.Shader.200-.patch | [PATCH 114/172] [Backport to 14][DebugInfo] Add NonSemantic.Shader.200 debug operations (#1976) Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186 The patch also adds Constantness requirement for operands |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-26 | ||
| 0115-DebugInfo-Translate-inline-namespace-debug-info-1978.patch | [PATCH 115/172] [DebugInfo] Translate inline namespace debug info (#1978) In NonSemantic.Shader.DebugInfo.200 DebugLexicalBlock has Inline namespace parameter, which specifies if C/C++ namespace is inline or not. It allows us to save `exportSymbols` field of `DINamespace` metadata. Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186/ |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-27 | ||
| 0116-DebugInfo-Fix-translation-of-Target-Function-operand.patch | [PATCH 116/172] [DebugInfo] Fix translation of Target Function operand (#1982) Before reading Target function name operand of `DebugFunction` we need to make sure it's the translation of appropriate debug extension. Otherwise, we can get in a situation, where we do have 11 operands, but the last one is not a `String` with name, but the `DebugFunctionDeclaration`. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-27 | ||
| 0117-Backport-to-14-NFC-DebugInfo-Rewrite-NonSemantic-Deb.patch | [PATCH 117/172] [Backport to 14][NFC][DebugInfo] Rewrite NonSemantic/DebugInfoProducer test There is a bug in -r -spirv-text mode in translation of Strings with spaces. Temporary avoid running such pipeline until proper fix is delivered. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-28 | ||
| 0118-Backport-to-14-DebugInfo-Fix-missing-2nd-operand-for.patch | [PATCH 118/172] [Backport to 14][DebugInfo] Fix missing 2nd operand for DebugImportedEntity (#1983) It will be still missing for OpenCL debug info, but for NonSemantic the correct behavior is preserved. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-02 | ||
| 0119-do-not-rely-on-version-of-compiler-being-VER.0.0.patch | [PATCH 119/172] do not rely on version of compiler being $VER.0.0 | Stanley Gambarin <stanley.gambarin@intel.com> | no | 2023-05-09 | ||
| 0120-Backport-to-14-Fix-SPIRV-Friendly-IR-mangling-for-op.patch | [PATCH 120/172] [Backport to 14] Fix SPIRV Friendly IR mangling for opcodes from cl_khr_integer_do_product (#2014) (#2017) | Mateusz Chudyk <mateuszchudyk@gmail.com> | no | 2023-06-07 | ||
| 0121-Remove-travis-from-llvm-14-branch-2048.patch | [PATCH 121/172] Remove travis from llvm 14 branch (#2048) CI is running on github actions |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-06-12 | ||
| 0122-DebugInfo-Translate-DW_OP_LLVM_arg-with-more-then-on.patch | [PATCH 122/172] [DebugInfo] Translate DW_OP_LLVM_arg with more then one parameter (#1987) DebugOperation is updated adding: If Operation is Arg, the DebugOperation has only one optional operand, which is <id> of a non-debug instruction whose value is used as an argument of a debug expression. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-04 | ||
| 0123-DebugInfo-Support-translation-of-DebugSourceContinue.patch | [PATCH 123/172] [DebugInfo] Support translation of DebugSourceContinued (#1993) Max length of SPIRV instruction is 65535 words by specification. DebugSourceContinued helps to overcome the limitation and specify full source code text by continuing the string from the previous DebugSource(Continued)instruction. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugSourceContinued |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-05 | ||
| 0124-DebugInfo-Fix-translation-of-DebugSource-Text-argume.patch | [PATCH 124/172] [DebugInfo] Fix translation of DebugSource Text argument (#2003) Handle the case when we have `DebugInfoNone` for the Text argument which is usually expected to be `OpString`. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-09 | ||
| 0125-DebugInfo-Translate-checksum-info-inside-DebugSource.patch | [PATCH 125/172] [DebugInfo] Translate checksum info inside DebugSource instruction (#1996) It's done in scope of NonSemantic.Shader.200.DebugInfo spec to have a proper solution for translation of checksum info (instead of the W/A done for OpenCL DebugInfo spec in #936) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-19 | ||
| 0126-DebugInfo-Fix-CU-translation-when-GV-goes-before-CU-.patch | [PATCH 126/172] [DebugInfo] Fix CU translation when GV goes before CU (#2010) Translation of DebugInfo compilation units and entry points moved before translation of GVs. In other case we might end up in a situation when while quering for CUs we find none of them. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-19 | ||
| 0127-DebugInfo-Support-translation-of-DebugBuildIdentifie.patch | [PATCH 127/172] [DebugInfo] Support translation of DebugBuildIdentifier/DebugStoragePath instruction (#1977) LLVM compileUnit dwoId is translated to/from DebugBuildIdentifier. LLVM compileUnit splitDebugFilename is translated to/from DebugStoragePath. Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugBuildIdentifier https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugStoragePath |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-05-19 | ||
| 0128-DebugInfo-Fix-DebugTypeVector-Component-Count-2006.patch | [PATCH 128/172] [DebugInfo] Fix DebugTypeVector Component Count (#2006) It should be OpConstant |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-19 | ||
| 0129-DebugInfo-Relax-consumer-checks-for-checksum-info-20.patch | [PATCH 129/172] [DebugInfo] Relax consumer checks for checksum info (#2011) It's a follow up for https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1996 since I couldn't update the PR |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-28 | ||
| 0130-DebugInfo-Add-Flags-operand-for-DebugTypeBasic-for-N.patch | [PATCH 130/172] [DebugInfo] Add Flags operand for DebugTypeBasic for NonSemantic spec (#2034) Flags operand is not optional, fill it with DebugInfoNone value (see #1965 for clarifications why it could not be generated by clang or by LLVM environment). |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-02 | ||
| 0131-DebugInfo-Adjust-TypeMember-for-NonSemantic-spec-203.patch | [PATCH 131/172] [DebugInfo] Adjust TypeMember for NonSemantic spec (#2033) It no longer has a Scope (parent) parameter. It results in several changes including how to determine DIBuilder to use for debug info generation. The patch also fixes a bug of incorrect debug info assignment in case of recursion DebugInfo inst generation. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-06-02 | ||
| 0132-Only-generate-BuildIdentifier-if-non-semantic-debug-.patch | [PATCH 132/172] Only generate BuildIdentifier if non-semantic debug is enabled (#2040) Only generate BuildIdentifier and StoragePath if non-semantic debug is enabled |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-06-09 | ||
| 0133-Implement-DebugLine-and-DebugNoLine-2012.patch | [PATCH 133/172] Implement DebugLine and DebugNoLine (#2012) Implement DebugLine/DebugNoLine for NonSemantic.Shader.DebugInfo.100 and NonSemantic.Shader.DebugInfo.200. Updated test/DebugInfo/NonSemantic/Shader200/DebugInfoStringType.ll to test these changes. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-06-09 | ||
| 0134-DebugInfo-Adjust-TypeInheritance-for-NonSemantic-spe.patch | [PATCH 134/172] [DebugInfo] Adjust TypeInheritance for NonSemantic spec (#2039) It does not have Child parameter comparing to OpenCL specification. https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugTypeInheritance |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-09 | ||
| 0135-DebugInfo-Add-Column-parameter-to-DebugInlinedAt-ins.patch | [PATCH 135/172] [DebugInfo] Add Column parameter to DebugInlinedAt instruction (#2042) The change is done as a part of NonSemantic.Shader.200 spec, and the new arguments for the instructions will look like: | \<id\> Line| \<id\> Column| \<id\> Scope| Optional\<id\> Inlined| |--------|--------|--------|--------| |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-11 | ||
| 0136-DebugInfo-Add-debug-info-for-bitfield-members-1907.patch | [PATCH 136/172] [DebugInfo] Add debug info for bitfield members (#1907) | asudarsa <arvind.sudarsanam@intel.com> | no | 2023-06-13 | ||
| 0137-Regenerate-debug-info-for-tests-with-clang-14.0.patch | [PATCH 137/172] Regenerate debug info for tests with clang 14.0 | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2023-06-19 | ||
| 0138-Fix-SourceContinued-translation-and-clang-format-tid.patch | [PATCH 138/172] Fix SourceContinued translation and clang-format/tidy warnings | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2023-06-19 | ||
| 0139-Backport-to-14-NFC-Remove-JointMatrixINTEL-W-S-1658.patch | [PATCH 139/172] [Backport to 14] [NFC] Remove JointMatrixINTEL W/S (#1658) It's not longer needed after https://github.com/intel/llvm/pull/6535 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-10-24 | ||
| 0140-Backport-to-15-Split-JointMatrixMadINTEL-instruction.patch | [PATCH 140/172] [Backport to 15] Split JointMatrixMadINTEL instruction into 4 (#1833) JointMatrixMadINTEL will stand for signed/signed Matrix type JointMatrixSUMadINTEL will stand for signed/signed Matrix type JointMatrixUSMadINTEL will stand for unsigned/signed Matrix type JointMatrixUUMadINTEL will stand for unsigned/unsigned Matrix type Spec update: intel/llvm#8175 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-02-15 | ||
| 0141-Backport-to-14-Adjust-builtin-variable-tracking-to-s.patch | [PATCH 141/172] [Backport to 14] Adjust builtin variable tracking to support i8 geps. (#1892) (#2066) The existing logic for the replacement of builtin variables with calls to functions relies on relatively brittle tracking that is broken when opaque pointers is turned on, and will be even more thoroughly broken if/when typed geps are replaced with i8 geps or ptradd. This patch replaces that logic with a less brittle variant that is able to handle any sequence of bitcast, gep, or addrspacecast instructions between the global variable and the ultimate load instruction. It still will error out if the variable is used in too insane of a fashion (say, trying to load an i32 out of the i64, or a misaligned vector type). |
Leonid Satanovskiy <leonid.satanovskiy@intel.com> | no | 2023-07-03 | ||
| 0142-Backport-to-14-DebugInfo-Fix-translation-of-SPV_INTE.patch | [PATCH 142/172] [Backport to 14][DebugInfo] Fix translation of SPV_INTEL_debug_module extension When NonSemantic.Shader.100 debug info is enabled. The related tests cases are enabled back. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-07-03 | ||
| 0143-Backport-to-14-DebugInfo-Cache-CU-value-translated-o.patch | [PATCH 143/172] [Backport to 14][DebugInfo] Cache CU value translated outside of usual flow Compilation unit can be translated earlier, e.g. in `transEntryPoint()`. We should save the translated LLVM value to be used further. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-07-07 | ||
| 0144-Backport-to-14-DebugInfo-Fix-DebugTypeSubrange-param.patch | [PATCH 144/172] [Backport to 14][DebugInfo] Fix DebugTypeSubrange parameters order Count should be the 3rd parameter. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-07-12 | ||
| 0145-Backport-to-14-DebugInfo-Correctly-use-cached-DIComp.patch | [PATCH 145/172] [Backport to 14][DebugInfo] Correctly use cached DICompilationUnit Followup for https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/2072 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-07-17 | ||
| 0146-Adjust-Source-Lang-Literal-logic-to-support-multiple.patch | [PATCH 146/172] Adjust "Source Lang Literal" logic to support multiple CompileUnits (#2100) This commit changes "Source Lang Literal" flag from simple a scalar value to a vector of pairs: (compile unit, source language). |
Mateusz Chudyk <mateusz.chudyk@intel.com> | no | 2023-08-01 | ||
| 0147-DebugInfo-Fix-parent-scope-index-for-ImportedEntity-.patch | [PATCH 147/172] [DebugInfo] Fix parent scope index for ImportedEntity (#2095) (#2110) Should be more cautious with inline namespaces |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-08-01 | ||
| 0148-Fix-delete-of-functions-that-becomes-unused-2109-211.patch | [PATCH 148/172] Fix delete of functions that becomes unused (#2109) (#2114) After the first loop of deleting instructions in ValuesToDelete, deleted instructions in ValuesToDelete are in an unstable state. Then in the second loop of deleting, dyn_cast to GlobalValue could return true for an instruction and double eraseFromParent causes crash. Global values in ValuesToDelete are functions. Unused functions are deleted by eraseUselessFunctions anyway. (cherry picked from commit aea1ac74ed4301df12adbffff535f72f37d0bb13) |
Wenju He <wenju.he@intel.com> | no | 2023-08-05 | ||
| 0149-Support-for-SPV_INTEL_cache_controls-2148.patch | [PATCH 149/172] Support for SPV_INTEL_cache_controls (#2148) Cherry-pick of KhronosGroup/SPIRV-LLVM-Translator#2140 |
Andrzej Ratajewski <andrzej.ratajewski@intel.com> | no | 2023-09-12 | ||
| 0150-Initial-implementation-of-SPV_KHR_cooperative_matrix.patch | [PATCH 150/172] Initial implementation of SPV_KHR_cooperative_matrix extension (#2099) The intention is to replace existing SPV_INTEL_joint_matrix extension to the Khronos one in future. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_cooperative_matrix.asciidoc |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-08-02 | ||
| 0151-Test-access-and-store-operations-for-cooperative-mat.patch | [PATCH 151/172] Test access and store operations for cooperative matrix (#2117) For now, the reverse translation is not resolved properly, so we test only forward translation here. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-08-09 | ||
| 0152-Test-OpCooperativeMatrixLengthKHR-2135.patch | [PATCH 152/172] Test OpCooperativeMatrixLengthKHR (#2135) For now we are violating the specification by passing Matrix Id instead of Matrix Type Id. Place for improvement - to come up with the way to translate only the type. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-08-24 | ||
| 0153-Test-conversion-instructions-for-TypeCooperativeMatr.patch | [PATCH 153/172] Test conversion instructions for TypeCooperativeMatrixKHR (#2137) | Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-08-25 | ||
| 0154-Test-arithmetic-instructions-for-TypeCooperativeMatr.patch | [PATCH 154/172] Test arithmetic instructions for TypeCooperativeMatrixKHR (#2156) Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_cooperative_matrix.asciidoc |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-09-18 | ||
| 0155-Adapt-tests-and-implementation-to-LLVM-14.patch | [PATCH 155/172] Adapt tests and implementation to LLVM 14 | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2023-09-15 | ||
| 0156-Reverse-translation-of-arithmetic-instructions-for-c.patch | [PATCH 156/172] Reverse translation of arithmetic instructions for cooperative matrixes (#2166) Implement translation via SPIR-V friendly calls, as: the LLVM instructions are not capable to accept target extension types; matrix arithmetic instructions require additional carry additional rules, which LLVM can not perform (for example while technically Add for vectors and (flattened) matrices is the same - yet for matrices we need to perform extra checks, also mul instruction is complitely different). As for now some BE would need to recognize and define what to do with a call to __spirv_FMul(matrixA, matrixB). Better option is to map such SPIR-V to an intrinsic or define an appropriate type in LLVM (hence defining rules for GEP and other instructions) , but it's off the table now. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-10-04 | ||
| 0157-Reverse-translation-of-access-load-store-operations-.patch | [PATCH 157/172] Reverse translation of access + load/store operations for cooperative matrix (#2165) Implement translation via SPIR-V friendly calls, as: the LLVM instructions are not capable to accept target extension types; cooperative matrix is an opaque object and accessing elements is implementation defined, hence we can't use GEP to which AccessChain naturally maps, since GEP has a different meaning. As for now some BE would need to recognize and define what to do with a call to __spirv_AccessChain(matrix, index). Better option is to map such SPIR-V to an intrinsic or define an appropriate type in LLVM (hence defining rules for GEP and other instructions) , but it's off the table now. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-10-04 | ||
| 0158-Backport-to-14-Backport-spirv-preserve-auxdata-chang.patch | [PATCH 158/172] [Backport to 14] Backport spirv-preserve-auxdata changes (#2178) Backport the below changes to 14: f729c49 89d658c 9823690 d498f48 d24b9c6 I made the following changes that are not in the original changes: Use llvm::Optional instead of std::optional Port tests to not use opaque pointers and related flags Fix patch fail due to missing unrelated function in this branch |
Nick Sarnie <sarnex@users.noreply.github.com> | no | 2023-10-13 | ||
| 0159-Backport-to-14-OpaquePointers-Handle-llvm.memset-int.patch | [PATCH 159/172] [Backport to 14][OpaquePointers] Handle llvm.memset intrinsic mangling mismatches. (#2181) Original change: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/bdd765263a0a7184dbd18fe5396313802f731e25 Non-constant @llvm.memset calls are presently lowered by generating synthetic functions with the mangled name of memset. However, the reader tries to use this name to generate the intrinsic call again. This causes verification issues if the SPIRVWriter and SPIRVReader do not agree on whether or not to use opaque pointers. This change uses the actual type of the function (which will take into account whether or not it is in opaque pointer mode) to generate the LLVM intrinsic name, fixing the mismatch issues. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-10-16 | ||
| 0160-Backport-to-14-Implement-support-for-SPV_KHR_shader_.patch | [PATCH 160/172] [Backport to 14] Implement support for SPV_KHR_shader_clock (#2026) (#2203) Link to the spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_shader_clock.asciidoc |
Aleksander Mielczarek <110471911+naxiiv@users.noreply.github.com> | no | 2023-11-09 | ||
| 0161-Bckport-to-14-Add-JointMatrixGetElementCoordINTEL-in.patch | [PATCH 161/172] [Bckport to 14] Add JointMatrixGetElementCoordINTEL instruction (#2225) The instruction returns (Row, Column) coordinate of dynamically selected element of a matrix Updated version of the spec is here intel/llvm#8175 Instruction correctness checks will be added later among non-backward compatible changes. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-11-20 | ||
| 0162-Backport-to-14-Fix-SPIR-V-global-to-function-replace.patch | [PATCH 162/172] [Backport to 14] Fix SPIR-V global to function replacement for differing load types (#2160) (#2242) In some cases, we will see IR with the following @__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32 ... %0 = load <6 x i32>, ptr addrspace(1) @__spirv_BuiltInGlobalInvocationId, align 32 %1 = extractelement <6 x i32> %0, i64 0 Note the global type and load type are different. Change the handling of vector loads from vector globals to reconstruct the global vector type and then bitcast to the load type. Thanks to @jcranmer-intel for helping me find the simplest solution. |
Maksim Shelegov <maksim.shelegov@intel.com> | no | 2023-11-29 | ||
| 0163-SPV-LLVM-Fix-global-c-dtors-type-if-SPV-is-from-opaq.patch | [PATCH 163/172] [SPV->LLVM] Fix global c/dtors type if SPV is from opaque type LLVM (#2280) When SPV is generated from LLVM IR with opaque pointer enabled, ctor function in global ctors has opaque pointer type rather than function type. When translating the SPV back to LLVM IR with typed pointer like in LLVM 14, ctor function type is casted to i8* pointer in the global ctors initializer. This results in error in LLVM verifier. This PR fixes the issue by removing the cast. |
Wenju He <wenju.he@intel.com> | no | 2023-12-28 | ||
| 0164-Backport-to-14-Update-LongConstantCompositeINTEL-to-.patch | [PATCH 164/172] [Backport to 14] Update LongConstantCompositeINTEL to LongCompositesINTEL capability after Headers change (#2311) The original change: 0166a0f Bump SPIRV-Headers to 1c6bb2743599e6eb6f37b2969acc0aef812e32e3 replace internal SPV_INTEL_long_composites ext with the published SPV_INTEL_long_composites don't rename extension for now Also fix behavior introduced by 70e9de0 which causes assertion after updating Headers version This fixes the following failure: llvm/lib/IR/Type.cpp:729: static llvm::PointerType* llvm::PointerType::get(llvm::Type*, unsigned int): Assertion 'isValidElementType(EltTy) && "Invalid type for pointer element!"' failed. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2024-01-23 | ||
| 0165-Fix-reverse-translation-of-non-constant-values-of-Op.patch | [PATCH 165/172] Fix reverse translation of non-constant values of OpCompositeConstruct (#2256) This patch introduces a way to use runtime values for structure fields. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-12-15 | ||
| 0166-Fix-reverse-translation-of-non-constant-values-of-Op.patch | [PATCH 166/172] Fix reverse translation of non-constant values of OpCompositeConstruct pt.2 (#2296) This patch introduces a way to use runtime values for array and vector types. It continues #2256 |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2024-01-09 | ||
| 0167-Fix-GEP-generation.patch | [PATCH 167/172] Fix GEP generation | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2024-01-11 | ||
| 0168-Backport-to-14-DebugInfo-Preserve-DIExpression-in-DI.patch | [PATCH 168/172] [Backport to 14][DebugInfo] Preserve DIExpression in DIGlobalVariableExpression (#2323) Ensure that SPIR-V that uses a DebugGlobalVariable's Variable field to hold an Expression can be reverse translated. A Variable field can be used to hold an Expression in order to preserve a DIExpression in a DIGlobalVariableExpression in LLVM IR. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2024-01-31 | ||
| 0169-Bckport-to-14-SPV-SPV-IR-Fix-image-builtin-mangling-.patch | [PATCH 169/172] [Bckport to 14][SPV -> SPV-IR] Fix image builtin mangling of unsigned type (#2273) (#2327) Return type of image read and Texel type of image write builtins may be unsigned. Before this PR, the builtin names in SPIR-V Friendly IR were always mangled with signed type. (cherry picked from commit e9b95fb) |
Wenju He <wenju.he@intel.com> | no | 2024-01-31 | ||
| 0170-Backport-to-14-Translate-atomicrmw-fadd-into-AtomicF.patch | [PATCH 170/172] [Backport to 14] Translate atomicrmw fadd into AtomicFAddEXT (#1757) | Nick Sarnie <sarnex@users.noreply.github.com> | no | 2022-12-07 | ||
| 0171-Backport-to-14-Translate-atomicrmw-fsub-into-FNegate.patch | [PATCH 171/172] [Backport to 14] Translate atomicrmw fsub into FNegate and AtomicFAddEXT (#1780) | Nick Sarnie <sarnex@users.noreply.github.com> | no | 2022-12-22 | ||
| 0172-Backport-to-14-add-initial-f16-type-support-for-atom.patch | [PATCH 172/172] [Backport to 14] add initial f16 type support for atomicrmw in llvm-spirv translator (#2210) This PR aims to add f16 type support for atomicrmw in llvm-spirv translator, with the reference to the extension documented in [1]. There are two concerns related to the subject: SPIRVAtomicFAddEXTInst::getRequiredExtension() should return a list of required extension to support the requirement to list both SPV_EXT_shader_atomic_float16_add and SPV_EXT_shader_atomic_float_add extensions in the module (see "Extension Name" section of the ref [1]). However, the return type is std::optional<ExtensionID> and returning a vector would need a bigger rework. Including SPV_EXT_shader_atomic_float16_add into --spirv-ext argument of llvm-spirv doesn't result in producing the correspondent capability (AtomicFloat16AddEXT) and extension in a SPIRV output. $ llvm-spirv AtomicFAddEXT.ll.tmp.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add -o AtomicFAddEXT.ll.tmp.spv $ llvm-spirv -to-text AtomicFAddEXT.ll.tmp.spv -o /dev/stdout ... 2 Capability AtomicFloat32AddEXT 2 Capability AtomicFloat64AddEXT 9 Extension "SPV_EXT_shader_atomic_float_add" ... This prevents extending the test case of AtomicFAddEXT.ll in EXT/SPV_EXT_shader_atomic_float. References: [1] https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_shader_atomic_float16_add.asciidoc |
Vyacheslav Levytskyy | no | 2023-11-14 | ||
| 0173-Backport-to-14-support-joint-matrix-prefetch-2359.patch | [PATCH 173/177] [Backport to 14] support joint matrix prefetch (#2359) This PR aims to introduce CooperativeMatrixPrefetchINTEL capability and operation, and make initial introduction of entities in llvm-spirv translator. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2024-02-14 | ||
| 0174-Backport-to-14-Fix-allowed-types-for-OpConstantNull-.patch | [PATCH 174/177] [Backport to 14] Fix allowed types for OpConstantNull (#2361) The SPIR-V Specification allows `OpConstantNull` types to be scalar or vector booleans, integers, or floats. Update an assert for this and add a SPIR-V -> LLVM IR test. (cherry picked from commit 9ec969c1c379bde69522b3b9278e5f7aa1a2c9f9) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2024-02-15 | ||
| 0175-DebugInfo-Fix-SPIR-V-consumption-of-DebugInfoNone-fo.patch | [PATCH 175/177] [DebugInfo] Fix SPIR-V consumption of DebugInfoNone for debug types (#2341) OpenCL and NonSemantic DebugInfo specifications are flexible in terms of allowing any debug information be replaced with DebugInfoNone, so various of SPIR-V producers follow that and generate it for base types of several debug instructions, leaving SPIR-V consumers to handle this. By default the translator replaces missing debug info with tag: null, which is in most cases correct. Yet, there are situations, where it's not allowed by both LLVM and DWARF, for example for DW_TAG_array_type DWARF spec sets, that DW_AT_type attribute is mandatory. For such cases new transNonNullDebugType wrapper function was added to the translator, generating "DIBasicType(tag: DW_TAG_unspecified_type, name: "SPIRV unknown type")" where DebugInfoNone was used as the type. This function doesn't replace all calls to transDebugInst<DIType> as there are cases, where we can generate null type, for example DWARF doesn't require it for DW_TAG_typedef, hence I'm not changing translation flow in this case. Additionally to this, while DWARF requires type attribute for DW_TAG_pointer_type, LLVM does not, hence I'm not changing translation flow in this case as well. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2024-02-10 | ||
| 0176-NFC-Fix-DebugTypeVector-test-2347.patch | [PATCH 176/177] [NFC] Fix DebugTypeVector test (#2347) It should have tested DebugInfoNone base type |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2024-02-12 | ||
| 0177-Back-port-of-some-patches-from-llvm16-version-of-Tra.patch | [PATCH 177/177] Back-port of some patches from llvm16 version of Translator. (#2371) * Backport from llvm16 branch: Support FPGA function !spirv.Decoration metadata Supporting the new FPGA kernel attribute pipelined needs the translator to handle !spirv.Decoration metadata on functions as well as on global variables. If the MD is found on the function, call the existing translation of metadata. * Backport from llvm16 branch: Implement RegisterMapInterfaceINTEL execution mode This PR adds the new execution mode RegisterMapInterfaceINTEL, see the Khronos SPIRV spec here: KhronosGroup/SPIRV-Registry#176 This execution mode allows specifying a 'register' based interface for FPGA kernels. * Backport from llvm16 branch: Implement SPIR-V support for max_reinvocation_delay attribute The attribute generates the llvm.loop.intel.max_reinvocation_delay.count metadata in LLVM IR. There is one positive integer literal operand denoting the maximum number of cycles allowed between loop invocations. * Backport from llvm18 branch: Support sycl_ext_oneapi_prefetch Handle new properties and decorate prefetch's arg. |
Fedor Veselovskiy <fedor.veselovsky@intel.com> | no | 2024-02-28 | ||
| 0178-Add-support-for-IAddCarry-SPIRV-instruction-2167.patch | [PATCH 178/179] Add support for IAddCarry SPIRV instruction (#2167) This commit implements bidirectional translation of the llvm.uadd.with.overflow and the IAddCarry intrinsic. Intrinsic llvm.uadd.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from IAddCarry needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-12 | ||
| 0179-Add-support-for-ISubBorrow-SPIRV-instruction-2168.patch | [PATCH 179/179] Add support for ISubBorrow SPIRV instruction (#2168) This commit implements bidirectional translation of the llvm.usub.with.overflow and the ISubBorrow intrinsic. Intrinsic llvm.usub.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from ISubBorrow needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-13 | ||
| visibility-hidden.patch | reduce the amount of symbols exposed by the library | Andreas Beckmann <anbe@debian.org> | yes |