| Patch | Description | Author | Forwarded | Bugs | Origin | Last update |
|---|---|---|---|---|---|---|
| 0001-Integer-dot-product-4x8-packed-translation-1654.patch | [PATCH 01/79] Integer dot product 4x8 packed translation (#1654) Changed the integer dot translation to use the correct function names (i.e. dot_4x8packed or dot_acc_sat_4x8packed) to translate them into proper OpCodes. Additionally removed unused variables from visitCallDot |
Jakub Czarnecki <jakub.czarnecki@intel.com> | no | 2022-10-17 | ||
| 0002-Add-support-for-split-barriers-extension-SPV_INTEL_s.patch | [PATCH 02/79] Add support for split barriers extension SPV_INTEL_split_barrier (#1424) (#1663) This PR adds support for split barriers and the SPV_INTEL_split_barrier extension. The related SPIR-V extension spec can be found here: * https://github.com/KhronosGroup/SPIRV-Registry/pull/136 The related OpenCL C extension spec can be found here: * https://github.com/KhronosGroup/OpenCL-Docs/pull/765 |
Haonan Yang <haonan.yang@intel.com> | no | 2022-10-20 | ||
| 0003-CI-Upgrade-to-Ubuntu-20.04.patch | [PATCH 03/79] [CI] Upgrade to Ubuntu 20.04 The Ubuntu 18.04 image is marked deprecated [1], so move to a newer image. [1] https://github.com/actions/runner-images |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2022-08-18 | ||
| 0004-NFC-Replace-getPointerElementType-in-SPIRVRegularize.patch | [PATCH 04/79] [NFC] Replace getPointerElementType in SPIRVRegularizeLLVM | "Sidorov, Dmitry" <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0005-NFC-Initialize-a-variable.patch | [PATCH 05/79] [NFC] Initialize a variable | "Sidorov, Dmitry" <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0006-Backport-to-15-Add-SPV_INTEL_masked_gather_scatter-e.patch | [PATCH 06/79] [Backport to 15] Add SPV_INTEL_masked_gather_scatter extension (#1580) (#1695) This extension allows TypeVector to have a Physical Pointer Type Component Type and introduces gather/scatter instructions. It will be useful for explicitly vectorized kernels. |
Stanley Gambarin <stanley.gambarin@intel.com> | no | 2022-11-08 | ||
| 0007-Backport-to-15-Translate-llvm.loop.unroll.full-metad.patch | [PATCH 07/79] [Backport to 15] Translate llvm.loop.unroll.full metadata (#1673) It can be generated via #pragma clang unroll(full) pragma. llvm.loop.unroll.full means attempt to do full unroll of the loop and disable the unrolling if the trip count is not known at compile time. Unroll mask to which it was previously mapped doesn't much the description. The way the patch represents it in SPIR-V is: Unroll mask + PartialCount mask with '1' parameter This patch also removes some overtesting for unroll metadata. This backports: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1664 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0008-Backport-to-15-Implement-SPV_INTEL_tensor_float32_co.patch | [PATCH 08/79] [Backport to 15] Implement SPV_INTEL_tensor_float32_conversion extension (#1656) (#1700) This extension adds conversion instruction from float to tensor float (TF32) data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead instruction below uses 32-bit float type to represent TF32 value. |
Stanley Gambarin <stanley.gambarin@intel.com> | no | 2022-11-11 | ||
| 0009-Backport-to-15-Fix-builtin-vars-translation.patch | [PATCH 09/79] [Backport to 15] Fix builtin vars translation The translator was crashing in case if builin GV was accessed via GEP without AS cast due to incorrect assumption. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-29 | ||
| 0010-Backport-to-15-Relax-OpenCL-extended-instruction-res.patch | [PATCH 10/79] [Backport to 15] Relax OpenCL extended instruction restrictions (#1755) * [Backport to 15] Relax OpenCL extended instruction restrictions (#1724) When VectorAnyINTEL capability is enabled, OpenCL extended instructions are able to work on vector types with any number of components greater then or equal to 2. * [Backport to 15] Translate LLVM intrinsics into native_* OpenCL instructions (#1729) When an intrinsic function is called with `afn` flag, it's allowed to substitute an approximate calculations. So the translator can emit native versions of OpenCL extended instructions. |
Stanley Gambarin <stanley.gambarin@intel.com> | no | 2022-12-08 | ||
| 0011-Backport-to-15-Add-SPV_EXT_relaxed_printf_string_add.patch | [PATCH 11/79] [Backport to 15] Add SPV_EXT_relaxed_printf_string_address_space extension The original change: #1749 The extension was added in https://github.com/KhronosGroup/SPIRV-Registry/pull/148 Starting from this PR SPV_INTEL_non_constant_addrspace_printf will be step by step deprecated. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-12-02 | ||
| 0012-Deprecate-SPV_INTEL_non_constant_addrspace_printf-ex.patch | [PATCH 12/79] Deprecate SPV_INTEL_non_constant_addrspace_printf extension (#1818) This change continues #1749. We are removing SPV_INTEL_non_constant_addrspace_printf extension in favor of SPV_EXT_relaxed_printf_string_address_space, which are basically the same. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-01-21 | ||
| 0013-Backport-to-15-Translate-readnone-attribute-as-funct.patch | [PATCH 13/79] [Backport to 15] Translate readnone attribute as function parameter attribute (#1697) Community restricted readnone, readonly and writeonly attributes to be only function parameter attributes. This patch aligns the translator with llvm.org. It also fixes a bug, when readnone attribute is being mapped to NoWrite SPIR-V function parameter attribute. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-08 | ||
| 0014-Backport-to-15-Put-memory-none-attribute-instead-of-.patch | [PATCH 14/79] [Backport to 15] Put memory(none) attribute instead of readnone (#1746) Instead of creating readnone attributes on each parameter of a function it's better to put just memory(none) which was recently introduced. See https://reviews.llvm.org/D135780 Co-authored by: Zou, Feng <feng.zou@intel.com> |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-11-29 | ||
| 0015-Allow-ReadNone-and-ReadOnly-as-Function-attributes.patch | [PATCH 15/79] Allow ReadNone and ReadOnly as Function attributes | Stanley Gambarin <stanley.gambarin@intel.com> | no | 2023-02-13 | ||
| 0016-Fix-mangling-of-opcodes-from-SPV_KHR_bit_instruction.patch | [PATCH 16/79] Fix mangling of opcodes from SPV_KHR_bit_instructions in SPV-IR (#1869) | Andrzej Ratajewski <andrzej.ratajewski@intel.com> | no | 2023-03-07 | ||
| 0017-Update-spirv-as-invocations-1933.patch | [PATCH 17/79] Update spirv-as invocations (#1933) After SPIRV-Tools commit 2e0f4b52 ("tools: refactorize tools flags parsing. (#5111)", 2023-02-27), spirv-as needs to be told explicitly when reading from stdin. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-31 | ||
| 0018-Backport-to-15-Initial-support-NonSemantic.Kernel.De.patch | [PATCH 18/79] [Backport to 15] Initial support NonSemantic.Kernel.DebugInfo.100 (#1846) This patch implements the initial support for the new debug specification NonSemantic.Kernel.DebugInfo.100. It also introduces support for the new debug instruction DISubrange. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-02-20 | ||
| 0019-Backport-to-15-DebugInfo-Add-Target-Function-optiona.patch | [PATCH 19/79] [Backport to 15][DebugInfo] Add Target Function optional parameter to DebugFunction (#1853) It's being added in KhronosGroup/SPIRV-Registry#186 In DWARF it's used in 'trampoline' functions generated for Fortran external function calls. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-02-23 | ||
| 0020-Backport-to-15-DebugInfo-Add-new-Source-Languages-ta.patch | [PATCH 20/79] [Backport to 15][DebugInfo] Add new Source Languages table used in DebugCompilationUnit (#1854) This extended source language table is used by DebugCompilationUnit instruction when the extension is enabled. It enables support for more languages than exists in a core specification. Enabling of Fortran language also allowed to fix FortranArray test that was originally XFAIL-ed in 9e234d9. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-02-23 | ||
| 0021-Backport-to-15-DebugInfo-Add-an-option-for-NonSemant.patch | [PATCH 21/79] [Backport to 15][DebugInfo] Add an option for NonSemantic.Shader.DebugInfo.100 (#1855) Under this option this extended instruction set will be implemented Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc NonSemantic.Shader.DebugInfo.200 when the name is stable |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-01 | ||
| 0022-Backport-to-15-DebugInfo-Add-DebugTypeArrayDynamic-t.patch | [PATCH 22/79] [Backport to 15][DebugInfo] Add DebugTypeArrayDynamic translation (#1871) This instruction describes a dynamic array, mostly for Fortran 90. Unlike DebugTypeArray it has Data Location, Associated, Allocated and Rank parameters. If the appropriate metadata parameters appear in LLVM IR in DW_TAG_array_type metadata, then such debug type becomes treated as dynamic array by the translator (of course if the appropriate extended instruction set is enabled). Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-08 | ||
| 0023-Backport-to-15-DebugInfo-Support-translation-of-DISt.patch | [PATCH 23/79] [Backport to 15][DebugInfo] Support translation of DIStringType (#1877) This type instruction describes a string, mostly for Fortran 90. Spec: KhronosGroup/SPIRV-Registry#186 |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-10 | ||
| 0024-Backport-to-15-DebugInfo-Support-translation-of-DIMo.patch | [PATCH 24/79] [Backport to 15][DebugInfo] Support translation of DIModule (#1878) This entity represents a module in the programming language, for example a Fortran module. Spec: KhronosGroup/SPIRV-Registry#186 The implementation is the same as for SPV_INTEL_debug_module extension. Spec for extension: https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_debug_module.asciidoc |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-13 | ||
| 0025-Backport-to-15-DebugInfo-Start-adopting-debug-info-i.patch | [PATCH 25/79] [Backport to 15][DebugInfo] Start adopting debug info instructions for NonSemantic set (#1887) List of changes: All Literal parameters of instructions in OpenCL.DebugInfo.100 are OpConstants in NonSemantic.Shader.DebugInfo.100 and NonSemantic.Shader.DebugInfo.200; SPV_KHR_non_semantic_info is being implicitly added for nonsemantic debug info; |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-21 | ||
| 0026-Backport-to-15-DebugInfo-Rename-NonSemantic.Kernel.D.patch | [PATCH 26/79] [Backport to 15][DebugInfo] Rename NonSemantic.Kernel.DebugInfo.100 (#1891) To NonSemantic.Shader.DebugInfo.200 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-03-20 | ||
| 0027-Backport-to-15-DebugInfo-Add-more-source-languages-a.patch | [PATCH 27/79] [Backport to 15][DebugInfo] Add more source languages and align to spec changes (#1894) | Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-21 | ||
| 0028-Backport-to-15-DebugInfo-Align-Instruction-names-to-.patch | [PATCH 28/79] [Backport to 15][DebugInfo] Align Instruction names to the specification (#1896) This patch fixes the discovered typos in Debug Instruction names, so we can generate spec-conformant SPIR-V module. https://registry.khronos.org/SPIR-V/specs/unified1/DebugInfo.html |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-03-23 | ||
| 0029-Rename-ConvertFToTF32INTEL-to-RoundFToTF32INTEL.patch | [PATCH 29/79] Rename ConvertFToTF32INTEL to RoundFToTF32INTEL Extension name will be preserved for a while for binary compatibility. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-04 | ||
| 0030-Backport-to-15-Preserve-invalid-SPIRV-source-lang-li.patch | [PATCH 30/79] [Backport to 15] Preserve invalid SPIRV source lang literal in module metadata (#1951) (#1980) Some SPIR-V producers generate invalid source language value (invalid = other than the enum values defined in spv::SourceLanguage). While in many cases this is rightly translated to DW_LANG_OpenCL, the original source language value should be preserved in LLVM module metadata for later use by LLVM IR consumers. |
Mateusz Chudyk <mateuszchudyk@gmail.com> | no | 2023-05-04 | ||
| 0031-Backport-to-15-Check-for-nullptr-from-getDbgInst-191.patch | [PATCH 31/79] [Backport to 15] Check for nullptr from getDbgInst (#1919) Ensure that ExprLB is non-NULL before using it. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-03-31 | ||
| 0032-DebugInfo-Add-DW_ATE_complex_float-translation-1946.patch | [PATCH 32/79] [DebugInfo] Add DW_ATE_complex_float translation (#1946) It's mapped on new Encoding value for DebugBasicType in NonSemantic.Shader.DebugInfo.200 spec. If another DebugInfo instruction set is specified - it's mapped to DW_TAG_unspecified_type Spec: KhronosGroup/SPIRV-Registry#186 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-12 | ||
| 0033-Backport-to-15-DebugInfo-Handle-null-value-of-DW_TAG.patch | [PATCH 33/79] [Backport to 15][DebugInfo] Handle null value of DW_TAG_template_value_parameter (#1956) It might be set as null in case if a function pointer is passed as auto template parameter. The patch also adds a test for a 'good' DW_TAG_template_value_parameter value for function pointers, just because this case was untested. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-14 | ||
| 0034-Backport-to-15-DebugInfo-Support-multiple-CompileUni.patch | [PATCH 34/79] [Backport to 15][DebugInfo] Support multiple CompileUnits (#1950) It's possible for LLVM IR module to contain multiple CU in case if this module is a result of llvm-link between two modules compiled for different languages and or compiled with different options. This patch introduces handling of such modules. std::unordered_map<SPIRVId, std::unique_ptr> BuilderMap was introduced to SPIR-V consumption part and std::unordered_map<const DICompileUnit *, SPIRVExtInst *> SPIRVCUMap was introduced to SPIR-V generation part to preserve Scope relations between DI metadata in SPIR-V and vice versa. Note, that DIBuilder has a single CU field and this class is not trivially copiable. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-19 | ||
| 0035-Backport-to-15-DebugInfo-Support-translation-of-Debu.patch | [PATCH 35/79] [Backport to 15][DebugInfo] Support translation of DebugFunctionDefinition instruction (#1961) DebugFunction does not have an Function Id operand in NonSemantic.Shader debug info specification. It's been replaced by the whole new DebugFunctionDefinition instruction to avoid forward references. This instruction must appear in the entry basic block of an OpFunction. Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugFunctionDefinition |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-20 | ||
| 0036-Backport-to-15-DebugInfo-Add-module-producer-info-fo.patch | [PATCH 36/79] [Backport to 15][DebugInfo] Add module producer info for NonSemantic.Shader.DebugInfo.200 (#1968) Keep existing W/A for other debug info specs, except NonSemantic.Shader.DebugInfo.100 |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-21 | ||
| 0037-NFC-Use-typed-pointers-for-null-function-pointers-de.patch | [PATCH 37/79] [NFC] Use typed pointers for null function pointers debug info (#1969) `PointerType::get(Context` will return typeless/opaque pointer. While it is OK for KHR translator since it's being built on top of LLVM trunk, where opaque pointers are enabled by default - it won't work for intel/llvm, where their generation is disabled. Upstream of https://github.com/intel/llvm/pull/9118 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-22 | ||
| 0038-DebugInfo-Fix-Composite-type-translation-for-NonSema.patch | [PATCH 38/79] [DebugInfo] Fix Composite type translation for NonSemantic spec (#1975) Tag should be OpConstant, not Literal. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-25 | ||
| 0039-DebugInfo-Add-Flag-parameter-to-DebugTypeBasic-1965.patch | [PATCH 39/79] [DebugInfo] Add Flag parameter to DebugTypeBasic (#1965) It can only be FlagUnknownPhysicalLayout. There is no way we can generate it LLVM environment and get use of it, hence the patch just ignores it if it come from another SPIR-V generator. In general, there are following possible debug flags for DIBasicType: BigEndian, LittleEndian and Artificial. There is not way that clang will ever generate them, but that can be produced by manually writing assembly and transforming it to LLVM IR. While it can be potential improvement for the future - I don't see it useful to add to the spec and implementation right now. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-26 | ||
| 0040-Backport-to-15-DebugInfo-Support-translation-of-Debu.patch | [PATCH 40/79] [Backport to 15][DebugInfo] Support translation of DebugEntryPoint instruction (#1973) This instruction is generated for DWARF `DISPFlagMainSubprogram` flag of function as well as for `spir_kernel` functions. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugEntryPoint |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-26 | ||
| 0041-Backport-to-15-DebugInfo-Add-NonSemantic.Shader.200-.patch | [PATCH 41/79] [Backport to 15][DebugInfo] Add NonSemantic.Shader.200 debug operations (#1976) Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186 The patch also adds Constantness requirement for operands |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-04-26 | ||
| 0042-DebugInfo-Translate-inline-namespace-debug-info-1978.patch | [PATCH 42/79] [DebugInfo] Translate inline namespace debug info (#1978) In NonSemantic.Shader.DebugInfo.200 DebugLexicalBlock has Inline namespace parameter, which specifies if C/C++ namespace is inline or not. It allows us to save `exportSymbols` field of `DINamespace` metadata. Spec: https://github.com/KhronosGroup/SPIRV-Registry/pull/186/ |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-27 | ||
| 0043-DebugInfo-Fix-translation-of-Target-Function-operand.patch | [PATCH 43/79] [DebugInfo] Fix translation of Target Function operand (#1982) Before reading Target function name operand of `DebugFunction` we need to make sure it's the translation of appropriate debug extension. Otherwise, we can get in a situation, where we do have 11 operands, but the last one is not a `String` with name, but the `DebugFunctionDeclaration`. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-27 | ||
| 0044-NFC-DebugInfo-Rewrite-NonSemantic-DebugInfoProducer-.patch | [PATCH 44/79] [NFC][DebugInfo] Rewrite NonSemantic/DebugInfoProducer test There is a bug in -r -spirv-text mode in translation of Strings with spaces. Temporary avoid running such pipeline until proper fix is delivered. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-04-28 | ||
| 0045-DebugInfo-Fix-missing-2nd-operand-for-DebugImportedE.patch | [PATCH 45/79] [DebugInfo] Fix missing 2nd operand for DebugImportedEntity (#1983) It will be still missing for OpenCL debug info, but for NonSemantic the correct behavior is preserved. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-02 | ||
| 0046-Restore-DebugInfoProducer.ll-test-to-original-state.patch | [PATCH 46/79] Restore DebugInfoProducer.ll test to original state | Stanley Gambarin <stanley.gambarin@intel.com> | no | 2023-05-05 | ||
| 0047-Backport-to-15-Fix-SPIRV-Friendly-IR-mangling-for-op.patch | [PATCH 47/79] [Backport to 15] Fix SPIRV Friendly IR mangling for opcodes from cl_khr_integer_do_product (#2014) (#2015) | Mateusz Chudyk <mateuszchudyk@gmail.com> | no | 2023-06-04 | ||
| 0048-Backport-to-15-NFC-Remove-JointMatrixINTEL-W-S-1658.patch | [PATCH 48/79] [Backport to 15] [NFC] Remove JointMatrixINTEL W/S (#1658) It's not longer needed after https://github.com/intel/llvm/pull/6535 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2022-10-24 | ||
| 0049-Backport-to-15-Split-JointMatrixMadINTEL-instruction.patch | [PATCH 49/79] [Backport to 15] Split JointMatrixMadINTEL instruction into 4 (#1833) JointMatrixMadINTEL will stand for signed/signed Matrix type JointMatrixSUMadINTEL will stand for signed/signed Matrix type JointMatrixUSMadINTEL will stand for unsigned/signed Matrix type JointMatrixUUMadINTEL will stand for unsigned/unsigned Matrix type Spec update: intel/llvm#8175 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-02-15 | ||
| 0050-DebugInfo-Support-translation-of-DebugSourceContinue.patch | [PATCH 50/79] [DebugInfo] Support translation of DebugSourceContinued (#1993) Max length of SPIRV instruction is 65535 words by specification. DebugSourceContinued helps to overcome the limitation and specify full source code text by continuing the string from the previous DebugSource(Continued)instruction. Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugSourceContinued |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-05 | ||
| 0051-DebugInfo-Fix-translation-of-DebugSource-Text-argume.patch | [PATCH 51/79] [DebugInfo] Fix translation of DebugSource Text argument (#2003) Handle the case when we have `DebugInfoNone` for the Text argument which is usually expected to be `OpString`. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-09 | ||
| 0052-DebugInfo-Translate-checksum-info-inside-DebugSource.patch | [PATCH 52/79] [DebugInfo] Translate checksum info inside DebugSource instruction (#1996) It's done in scope of NonSemantic.Shader.200.DebugInfo spec to have a proper solution for translation of checksum info (instead of the W/A done for OpenCL DebugInfo spec in #936) |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-05-19 | ||
| 0053-DebugInfo-Fix-CU-translation-when-GV-goes-before-CU-.patch | [PATCH 53/79] [DebugInfo] Fix CU translation when GV goes before CU (#2010) Translation of DebugInfo compilation units and entry points moved before translation of GVs. In other case we might end up in a situation when while quering for CUs we find none of them. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-19 | ||
| 0054-DebugInfo-Support-translation-of-DebugBuildIdentifie.patch | [PATCH 54/79] [DebugInfo] Support translation of DebugBuildIdentifier/DebugStoragePath instruction (#1977) LLVM compileUnit dwoId is translated to/from DebugBuildIdentifier. LLVM compileUnit splitDebugFilename is translated to/from DebugStoragePath. Specification: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugBuildIdentifier https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugStoragePath |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-05-19 | ||
| 0055-DebugInfo-Fix-DebugTypeVector-Component-Count-2006.patch | [PATCH 55/79] [DebugInfo] Fix DebugTypeVector Component Count (#2006) It should be OpConstant |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-19 | ||
| 0056-DebugInfo-Relax-consumer-checks-for-checksum-info-20.patch | [PATCH 56/79] [DebugInfo] Relax consumer checks for checksum info (#2011) It's a follow up for https://github.com/KhronosGroup/SPIRV-LLVM-Translator/pull/1996 since I couldn't update the PR |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-05-28 | ||
| 0057-DebugInfo-Add-Flags-operand-for-DebugTypeBasic-for-N.patch | [PATCH 57/79] [DebugInfo] Add Flags operand for DebugTypeBasic for NonSemantic spec (#2034) Flags operand is not optional, fill it with DebugInfoNone value (see #1965 for clarifications why it could not be generated by clang or by LLVM environment). |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-02 | ||
| 0058-DebugInfo-Adjust-TypeMember-for-NonSemantic-spec-203.patch | [PATCH 58/79] [DebugInfo] Adjust TypeMember for NonSemantic spec (#2033) It no longer has a Scope (parent) parameter. It results in several changes including how to determine DIBuilder to use for debug info generation. The patch also fixes a bug of incorrect debug info assignment in case of recursion DebugInfo inst generation. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-06-02 | ||
| 0059-Only-generate-BuildIdentifier-if-non-semantic-debug-.patch | [PATCH 59/79] Only generate BuildIdentifier if non-semantic debug is enabled (#2040) Only generate BuildIdentifier and StoragePath if non-semantic debug is enabled |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-06-09 | ||
| 0060-Implement-DebugLine-and-DebugNoLine-2012.patch | [PATCH 60/79] Implement DebugLine and DebugNoLine (#2012) Implement DebugLine/DebugNoLine for NonSemantic.Shader.DebugInfo.100 and NonSemantic.Shader.DebugInfo.200. Updated test/DebugInfo/NonSemantic/Shader200/DebugInfoStringType.ll to test these changes. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2023-06-09 | ||
| 0061-DebugInfo-Adjust-TypeInheritance-for-NonSemantic-spe.patch | [PATCH 61/79] [DebugInfo] Adjust TypeInheritance for NonSemantic spec (#2039) It does not have Child parameter comparing to OpenCL specification. https://github.com/KhronosGroup/SPIRV-Registry/blob/main/nonsemantic/NonSemantic.Shader.DebugInfo.100.asciidoc#DebugTypeInheritance |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-09 | ||
| 0062-DebugInfo-Add-Column-parameter-to-DebugInlinedAt-ins.patch | [PATCH 62/79] [DebugInfo] Add Column parameter to DebugInlinedAt instruction (#2042) The change is done as a part of NonSemantic.Shader.200 spec, and the new arguments for the instructions will look like: | \<id\> Line| \<id\> Column| \<id\> Scope| Optional\<id\> Inlined| |--------|--------|--------|--------| |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-06-11 | ||
| 0063-DebugInfo-Add-debug-info-for-bitfield-members-1907.patch | [PATCH 63/79] [DebugInfo] Add debug info for bitfield members (#1907) | asudarsa <arvind.sudarsanam@intel.com> | no | 2023-06-13 | ||
| 0064-Fix-SourceContinued-translation-and-clang-format-tid.patch | [PATCH 64/79] Fix SourceContinued translation and clang-format/tidy warnings | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2023-06-19 | ||
| 0065-Fix-clang-tidy-warnings.patch | [PATCH 65/79] Fix clang-tidy warnings | "Maksimova, Viktoria" <viktoria.maksimova@intel.com> | no | 2023-06-28 | ||
| 0066-Backport-to-15-OpaquePointers-Adjust-builtin-variabl.patch | [PATCH 66/79] [Backport to 15] [OpaquePointers] Adjust builtin variable tracking to support i8 geps (#2061) The existing logic for the replacement of builtin variables with calls to functions relies on relatively brittle tracking that is broken when opaque pointers is turned on, and will be even more thoroughly broken if/when typed geps are replaced with i8 geps or ptradd. This patch replaces that logic with a less brittle variant that is able to handle any sequence of bitcast, gep, or addrspacecast instructions between the global variable and the ultimate load instruction. It still will error out if the variable is used in too insane of a fashion (say, trying to load an i32 out of the i64, or a misaligned vector type). |
Mateusz Chudyk <mateuszchudyk@gmail.com> | no | 2023-07-03 | ||
| 0067-Adjust-Source-Lang-Literal-logic-to-support-multiple.patch | [PATCH 67/79] Adjust "Source Lang Literal" logic to support multiple CompileUnits (#2105) This commit changes "Source Lang Literal" flag from simple a scalar value to a vector of pairs: (compile unit, source language). |
Mateusz Chudyk <mateusz.chudyk@intel.com> | no | 2023-08-01 | ||
| 0068-Support-for-SPV_INTEL_cache_controls-2147.patch | [PATCH 68/79] Support for SPV_INTEL_cache_controls (#2147) Cherry-pick of KhronosGroup/SPIRV-LLVM-Translator#2140 |
Andrzej Ratajewski <andrzej.ratajewski@intel.com> | no | 2023-09-12 | ||
| 0069-Backport-to-15-Backport-spirv-preserve-auxdata-chang.patch | [PATCH 69/79] [Backport to 15] Backport spirv-preserve-auxdata changes (#2180) Backport the below changes to 15: f729c49 89d658c 9823690 d498f48 d24b9c6 I made the following changes that are not in the original changes: Use llvm::Optional instead of std::optional Port tests to not use opaque pointers and related flags Fix patch fail due to missing unrelated function in this branch |
Nick Sarnie <sarnex@users.noreply.github.com> | no | 2023-10-16 | ||
| 0070-Backport-to-15-OpaquePointers-Handle-llvm.memset-int.patch | [PATCH 70/79] [Backport to 15][OpaquePointers] Handle llvm.memset intrinsic mangling mismatches. (#2183) Original change: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/bdd765263a0a7184dbd18fe5396313802f731e25 Non-constant @llvm.memset calls are presently lowered by generating synthetic functions with the mangled name of memset. However, the reader tries to use this name to generate the intrinsic call again. This causes verification issues if the SPIRVWriter and SPIRVReader do not agree on whether or not to use opaque pointers. This change uses the actual type of the function (which will take into account whether or not it is in opaque pointer mode) to generate the LLVM intrinsic name, fixing the mismatch issues. |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2023-10-25 | ||
| 0071-Backport-to-15-Implement-support-for-SPV_KHR_shader_.patch | [PATCH 71/79] [Backport to 15] Implement support for SPV_KHR_shader_clock (#2026) (#2207) Link to the spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/KHR/SPV_KHR_shader_clock.asciidoc |
Aleksander Mielczarek <110471911+naxiiv@users.noreply.github.com> | no | 2023-11-09 | ||
| 0072-Backport-to-15-Add-JointMatrixGetElementCoordINTEL-i.patch | [PATCH 72/79] [Backport to 15] Add JointMatrixGetElementCoordINTEL instruction (#2226) The instruction returns (Row, Column) coordinate of dynamically selected element of a matrix Updated version of the spec is here intel/llvm#8175 Instruction correctness checks will be added later among non-backward compatible changes. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-11-20 | ||
| 0073-Backport-to-15-Fix-SPIR-V-global-to-function-replace.patch | [PATCH 73/79] [Backport to 15] Fix SPIR-V global to function replacement for differing load types (#2160) (#2243) In some cases, we will see IR with the following @__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32 ... %0 = load <6 x i32>, ptr addrspace(1) @__spirv_BuiltInGlobalInvocationId, align 32 %1 = extractelement <6 x i32> %0, i64 0 Note the global type and load type are different. Change the handling of vector loads from vector globals to reconstruct the global vector type and then bitcast to the load type. Thanks to @jcranmer-intel for helping me find the simplest solution. |
Maksim Shelegov <maksim.shelegov@intel.com> | no | 2023-11-29 | ||
| 0074-Backport-to-15-Update-LongConstantCompositeINTEL-to-.patch | [PATCH 74/79] [Backport to 15] Update LongConstantCompositeINTEL to LongCompositesINTEL capability after Headers change (#2310) The original change: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/0166a0fb86dc6c0e8903436bbc3a89bc3273ebc0 * Bump SPIRV-Headers to 1c6bb2743599e6eb6f37b2969acc0aef812e32e3 * replace internal SPV_INTEL_long_composites ext with the published SPV_INTEL_long_composites * don't rename extension for now |
Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2024-01-23 | ||
| 0075-Preserve-DIExpression-in-DIGlobalVariableExpression-.patch | [PATCH 75/79] Preserve DIExpression in DIGlobalVariableExpression (#2324) Ensure that SPIR-V that uses a DebugGlobalVariable's Variable field to hold an Expression can be reverse translated. A Variable field can be used to hold an Expression in order to preserve a DIExpression in a DIGlobalVariableExpression in LLVM IR. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2024-01-31 | ||
| 0076-Backport-to-15-Translate-atomicrmw-fadd-into-AtomicF.patch | [PATCH 76/79] [Backport to 15] Translate atomicrmw fadd into AtomicFAddEXT (#1757) | Nick Sarnie <sarnex@users.noreply.github.com> | no | 2022-12-07 | ||
| 0077-Backport-to-15-Translate-atomicrmw-fsub-into-FNegate.patch | [PATCH 77/79] [Backport to 15] Translate atomicrmw fsub into FNegate and AtomicFAddEXT (#1780) | Nick Sarnie <sarnex@users.noreply.github.com> | no | 2022-12-22 | ||
| 0078-Backport-to-15-add-initial-f16-type-support-for-atom.patch | [PATCH 78/79] [Backport to 15] add initial f16 type support for atomicrmw in llvm-spirv translator (#2210) This PR aims to add f16 type support for atomicrmw in llvm-spirv translator, with the reference to the extension documented in [1]. There are two concerns related to the subject: SPIRVAtomicFAddEXTInst::getRequiredExtension() should return a list of required extension to support the requirement to list both SPV_EXT_shader_atomic_float16_add and SPV_EXT_shader_atomic_float_add extensions in the module (see "Extension Name" section of the ref [1]). However, the return type is std::optional<ExtensionID> and returning a vector would need a bigger rework. Including SPV_EXT_shader_atomic_float16_add into --spirv-ext argument of llvm-spirv doesn't result in producing the correspondent capability (AtomicFloat16AddEXT) and extension in a SPIRV output. $ llvm-spirv AtomicFAddEXT.ll.tmp.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add -o AtomicFAddEXT.ll.tmp.spv $ llvm-spirv -to-text AtomicFAddEXT.ll.tmp.spv -o /dev/stdout ... 2 Capability AtomicFloat32AddEXT 2 Capability AtomicFloat64AddEXT 9 Extension "SPV_EXT_shader_atomic_float_add" ... This prevents extending the test case of AtomicFAddEXT.ll in EXT/SPV_EXT_shader_atomic_float. References: [1] https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_shader_atomic_float16_add.asciidoc |
Vyacheslav Levytskyy | no | 2023-11-14 | ||
| 0079-Backport-to-15-SPV-SPV-IR-Fix-image-builtin-mangling.patch | [PATCH 79/79] [Backport to 15][SPV -> SPV-IR] Fix image builtin mangling of unsigned type (#2273) (#2338) Return type of image read and Texel type of image write builtins may be unsigned. Before this PR, the builtin names in SPIR-V Friendly IR were always mangled with signed type. (cherry picked from commit e9b95fb) |
Wenju He <wenju.he@intel.com> | no | 2024-02-03 | ||
| 0080-Backport-to-15-Fix-allowed-types-for-OpConstantNull-.patch | [PATCH 80/85] [Backport to 15] Fix allowed types for OpConstantNull (#2361) The SPIR-V Specification allows `OpConstantNull` types to be scalar or vector booleans, integers, or floats. Update an assert for this and add a SPIR-V -> LLVM IR test. (cherry picked from commit 9ec969c1c379bde69522b3b9278e5f7aa1a2c9f9) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2024-02-15 | ||
| 0083-Add-support-for-IAddCarry-SPIRV-instruction-2167.patch | [PATCH 83/85] Add support for IAddCarry SPIRV instruction (#2167) This commit implements bidirectional translation of the llvm.uadd.with.overflow and the IAddCarry intrinsic. Intrinsic llvm.uadd.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from IAddCarry needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-12 | ||
| 0084-Add-support-for-ISubBorrow-SPIRV-instruction-2168.patch | [PATCH 84/85] Add support for ISubBorrow SPIRV instruction (#2168) This commit implements bidirectional translation of the llvm.usub.with.overflow and the ISubBorrow intrinsic. Intrinsic llvm.usub.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from ISubBorrow needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-13 | ||
| 0085-Backport-to-15-Handle-OpVectorShuffle-with-differing.patch | [PATCH 85/85] [Backport to 15] Handle OpVectorShuffle with differing vector sizes (#2391) (#2412) The SPIR-V to LLVM conversion would bail out when encountering an `OpVectorShuffle` whose vector operands differ in size. SPIR-V allows differing vector sizes, but LLVM's `shufflevector` does not. Remove the assert and insert an additional `shufflevector` to align the vector operands when needed. (cherry picked from commit 3df5e38250a6d7c50b58fbb0393be81d909487ff) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2024-03-06 | ||
| visibility-hidden.patch | reduce the amount of symbols exposed by the library | Andreas Beckmann <anbe@debian.org> | yes |