| Patch | Description | Author | Forwarded | Bugs | Origin | Last update |
|---|---|---|---|---|---|---|
| 0001-do-not-rely-on-version-of-compiler-being-VER.0.0-219.patch | [PATCH] do not rely on version of compiler being $VER.0.0 (#2195) | Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2023-10-26 | ||
| 0002-Backport-to-17-Update-LongConstantCompositeINTEL-to-.patch | [PATCH 2/5] [Backport to 17] Update LongConstantCompositeINTEL to LongCompositesINTEL capability after Headers change (#2258) (#2308) * Bump SPIRV-Headers to 1c6bb2743599e6eb6f37b2969acc0aef812e32e3 * replace internal SPV_INTEL_long_composites ext with the published SPV_INTEL_long_composites * don't rename extension for now This closes: https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/2261 |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2024-01-23 | ||
| 0003-Backport-to-17-add-initial-f16-type-support-for-atom.patch | [PATCH 3/5] [Backport to 17] add initial f16 type support for atomicrmw in llvm-spirv translator (#2210) (#2334) This PR aims to add f16 type support for atomicrmw in llvm-spirv translator, with the reference to the extension documented in [1]. There are two concerns related to the subject: SPIRVAtomicFAddEXTInst::getRequiredExtension() should return a list of required extension to support the requirement to list both SPV_EXT_shader_atomic_float16_add and SPV_EXT_shader_atomic_float_add extensions in the module (see "Extension Name" section of the ref [1]). However, the return type is std::optional<ExtensionID> and returning a vector would need a bigger rework. Including SPV_EXT_shader_atomic_float16_add into --spirv-ext argument of llvm-spirv doesn't result in producing the correspondent capability (AtomicFloat16AddEXT) and extension in a SPIRV output. $ llvm-spirv AtomicFAddEXT.ll.tmp.bc --spirv-ext=+SPV_EXT_shader_atomic_float_add,+SPV_EXT_shader_atomic_float16_add -o AtomicFAddEXT.ll.tmp.spv $ llvm-spirv -to-text AtomicFAddEXT.ll.tmp.spv -o /dev/stdout ... 2 Capability AtomicFloat32AddEXT 2 Capability AtomicFloat64AddEXT 9 Extension "SPV_EXT_shader_atomic_float_add" ... This prevents extending the test case of AtomicFAddEXT.ll in EXT/SPV_EXT_shader_atomic_float. References: [1] https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_shader_atomic_float16_add.asciidoc |
Mateusz Chudyk <mateusz.chudyk@intel.com> | no | 2024-02-01 | ||
| 0004-SPV-SPV-IR-Fix-image-builtin-mangling-of-unsigned-ty.patch | [PATCH 4/5] [SPV -> SPV-IR] Fix image builtin mangling of unsigned type (#2273) (#2336) Return type of image read and Texel type of image write builtins may be unsigned. Before this PR, the builtin names in SPIR-V Friendly IR were always mangled with signed type. (cherry picked from commit e9b95fbc3f58c7d8084620fd58b8bd936c640d37) |
Wenju He <wenju.he@intel.com> | no | 2024-02-01 | ||
| 0005-Backport-to-17-DebugInfo-Preserve-DIExpression-in-DI.patch | [PATCH 5/5] [Backport to 17][DebugInfo] Preserve DIExpression in DIGlobalVariableExpression (#2326) Ensure that SPIR-V that uses a DebugGlobalVariable's Variable field to hold an Expression can be reverse translated. A Variable field can be used to hold an Expression in order to preserve a DIExpression in a DIGlobalVariableExpression in LLVM IR. |
LU-JOHN <111294400+LU-JOHN@users.noreply.github.com> | no | 2024-02-05 | ||
| 0006-Backport-to-17-Fix-allowed-types-for-OpConstantNull-.patch | [PATCH 06/12] [Backport to 17] Fix allowed types for OpConstantNull (#2361) The SPIR-V Specification allows `OpConstantNull` types to be scalar or vector booleans, integers, or floats. Update an assert for this and add a SPIR-V -> LLVM IR test. (cherry picked from commit 9ec969c1c379bde69522b3b9278e5f7aa1a2c9f9) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2024-02-15 | ||
| 0007-Add-support-for-IAddCarry-SPIRV-instruction-2167.patch | [PATCH 07/12] Add support for IAddCarry SPIRV instruction (#2167) This commit implements bidirectional translation of the llvm.uadd.with.overflow and the IAddCarry intrinsic. Intrinsic llvm.uadd.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from IAddCarry needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-12 | ||
| 0008-Add-support-for-ISubBorrow-SPIRV-instruction-2168.patch | [PATCH 08/12] Add support for ISubBorrow SPIRV instruction (#2168) This commit implements bidirectional translation of the llvm.usub.with.overflow and the ISubBorrow intrinsic. Intrinsic llvm.usub.with.overflow returns struct which second element have a type of i1. The llvm type i1 is, in llvm-spirv, directly translated to BoolType. SPIRV specification requires that the composite which returns from ISubBorrow needs to have both elements of the same type. In result, current implementation is not compliant and should be considered temporary. |
bwlodarcz <bertrand.wlodarczyk@intel.com> | no | 2023-10-13 | ||
| 0009-Backport-to-17-Fix-function-with-unused-sret-paramet.patch | [PATCH 09/12] [Backport to 17] Fix function with unused sret parameter (#2381) (#2386) Usually sret parameters are accessed by a memory instruction, from which would tell SPIRVTypeScavenger which type to use for this function parameter. But if sret parameter is unused later in the module scavenger would fail attempting to deduce type from the mangled name. |
Dmitry Sidorov <dmitry.sidorov@intel.com> | no | 2024-03-05 | ||
| 0010-Backport-to-17-Support-SPV_INTEL_maximum_registers-e.patch | [PATCH 10/12] [Backport to 17] Support SPV_INTEL_maximum_registers extension (#2344) (#2393) Spec: KhronosGroup/SPIRV-Registry#235 |
Vlad Korovin <vladislav.korovin@intel.com> | no | 2024-03-06 | ||
| 0011-Backport-to-17-Handle-OpVectorShuffle-with-differing.patch | [PATCH 11/12] [Backport to 17] Handle OpVectorShuffle with differing vector sizes (#2391) (#2410) The SPIR-V to LLVM conversion would bail out when encountering an `OpVectorShuffle` whose vector operands differ in size. SPIR-V allows differing vector sizes, but LLVM's `shufflevector` does not. Remove the assert and insert an additional `shufflevector` to align the vector operands when needed. (cherry picked from commit 3df5e38250a6d7c50b58fbb0393be81d909487ff) |
Sven van Haastregt <sven.vanhaastregt@arm.com> | no | 2024-03-06 | ||
| 0012-LLVM-17-Remove-dependency-on-SPIRV-Headers-for-SPV_I.patch | [PATCH 12/12] [LLVM-17] Remove dependency on SPIRV-Headers for SPV_INTEL_maximum_registers (#2435) | Viktoria Maximova <viktoria.maksimova@intel.com> | no | 2024-03-13 | ||
| visibility-hidden.patch | reduce the amount of symbols exposed by the library | Andreas Beckmann <anbe@debian.org> | no |